IRIS
ALIOTO, MASSIMO BRUNO CRIS
 Distribuzione geografica
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Continente #
NA - Nord America 13.781
EU - Europa 9.506
AS - Asia 5.282
SA - Sud America 944
AF - Africa 169
Continente sconosciuto - Info sul continente non disponibili 9
OC - Oceania 9
AN - Antartide 1
Totale 29.701
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Nazione #
US - Stati Uniti d'America 13.664
GB - Regno Unito 2.413
CN - Cina 2.038
DE - Germania 1.889
SG - Singapore 1.447
RU - Federazione Russa 1.338
IE - Irlanda 1.064
UA - Ucraina 948
BR - Brasile 797
FR - Francia 637
SE - Svezia 523
HK - Hong Kong 480
VN - Vietnam 434
KR - Corea 299
FI - Finlandia 226
IT - Italia 184
IN - India 159
ES - Italia 120
TR - Turchia 104
AR - Argentina 65
NG - Nigeria 54
BD - Bangladesh 51
CA - Canada 51
IQ - Iraq 48
ZA - Sudafrica 42
MX - Messico 32
PL - Polonia 32
JP - Giappone 26
ID - Indonesia 24
NL - Olanda 24
BE - Belgio 22
PK - Pakistan 22
MA - Marocco 17
VE - Venezuela 16
CL - Cile 15
EG - Egitto 15
UZ - Uzbekistan 15
PY - Paraguay 14
SA - Arabia Saudita 14
EC - Ecuador 13
AT - Austria 11
RO - Romania 11
AZ - Azerbaigian 10
CO - Colombia 10
IR - Iran 10
NP - Nepal 10
PH - Filippine 10
EU - Europa 9
JO - Giordania 9
TN - Tunisia 9
AU - Australia 8
CZ - Repubblica Ceca 8
PE - Perù 8
TW - Taiwan 8
AE - Emirati Arabi Uniti 7
BG - Bulgaria 7
CH - Svizzera 7
GR - Grecia 7
KE - Kenya 7
EE - Estonia 6
LT - Lituania 6
MY - Malesia 6
CR - Costa Rica 5
CY - Cipro 5
DZ - Algeria 5
IL - Israele 5
JM - Giamaica 5
KZ - Kazakistan 5
TH - Thailandia 5
AM - Armenia 4
BB - Barbados 4
BH - Bahrain 4
CI - Costa d'Avorio 4
DO - Repubblica Dominicana 4
OM - Oman 4
PT - Portogallo 4
TT - Trinidad e Tobago 4
UY - Uruguay 4
HN - Honduras 3
QA - Qatar 3
RS - Serbia 3
AL - Albania 2
AO - Angola 2
ET - Etiopia 2
GA - Gabon 2
GT - Guatemala 2
HU - Ungheria 2
IM - Isola di Man 2
KG - Kirghizistan 2
KN - Saint Kitts e Nevis 2
LA - Repubblica Popolare Democratica del Laos 2
LB - Libano 2
LK - Sri Lanka 2
MD - Moldavia 2
NI - Nicaragua 2
SN - Senegal 2
SY - Repubblica araba siriana 2
TZ - Tanzania 2
AQ - Antartide 1
BA - Bosnia-Erzegovina 1
Totale 29.676
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Città #
Southend 2.199
Fairfield 1.930
Dallas 1.257
Ashburn 1.088
Dublin 1.062
Houston 1.037
Woodbridge 924
Jacksonville 772
Seattle 760
Chandler 735
Singapore 734
Wilmington 667
Cambridge 665
Hong Kong 458
Santa Clara 453
Ann Arbor 385
Beijing 374
Hefei 326
Princeton 316
Moscow 299
Seoul 295
Nanjing 277
The Dalles 252
San Jose 159
Ho Chi Minh City 141
Lauterbourg 141
Los Angeles 134
Hanoi 127
San Diego 119
Málaga 107
Boardman 98
Nanchang 92
Council Bluffs 82
Buffalo 79
Izmir 79
Shenyang 77
San Mateo 71
Helsinki 59
Hebei 51
São Paulo 51
Abuja 50
Siena 50
Kunming 46
New York 46
Bengaluru 43
Tianjin 42
Jiaxing 40
London 40
Shanghai 40
Changsha 34
Columbus 30
Guangzhou 29
Johannesburg 29
Mestre 28
Zhengzhou 27
Haiphong 26
Redondo Beach 26
Chicago 25
Frankfurt am Main 25
Warsaw 25
Orem 24
Norwalk 23
Chennai 22
Jinan 22
Hangzhou 20
Toronto 20
Belo Horizonte 19
Dearborn 19
Brooklyn 18
Brussels 18
Baghdad 17
Da Nang 17
Rio de Janeiro 17
San Francisco 17
Tokyo 17
Munich 16
Ningbo 16
Stockholm 16
Changchun 14
Lanzhou 14
Manchester 14
Porto Alegre 13
New Delhi 12
Redwood City 12
Tashkent 12
Curitiba 11
Tappahannock 11
Baku 10
Brasília 10
Campinas 10
Denver 10
Dhaka 10
Montreal 10
Mumbai 10
Philadelphia 10
Shenzhen 10
Vienna 10
Boston 9
Erbil 9
Jundiaí 9
Totale 20.211
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Nome #
Mixed Full Adder Topologies for High-Performance Low-Power Arithmetic Circuits 456
A Feedback Strategy to Improve the Entropy of a Chaos-Based Random Bit Generator 348
A Class of Maximum-Period Nonlinear Congruential Generators Derived From the Rényi Chaotic Map 304
A scalable low-entropy detector to counteract the parameter variability effects in TRBGs 273
Evaluation of Energy Consumption in RC Ladder Circuits Driven by a Ramp Input 271
A technique to design high entropy chaos-based true random bit generators 271
A general power model of Differential Power Analysis attacks to static logic circuits 270
A general model of DPA attacks to precharged busses in symmetric-key cryptographic algorithms 266
Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial 265
Implementation Efficient Maximum-Period Nonlinear Congruential Generators 264
A general model for differential power analysis attacks to static logic circuits 261
13.8 A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 259
Exploiting Locality to Improve Leakage Reduction in Embedded Drowsy I-Caches at Same Area/Speed 254
A Novel Back-Biasing Low-Leakage Technique for FinFET Forced Stacks 252
A Simple Keeper Topology to Reduce Delay Variations in Nanometer Domino Logic 252
A variability-tolerant feedback technique for throughput maximization of TRBGs with predefined entropy 251
Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under Process Variations 243
Modeling and Optimized Design of Current Mode MUX/XOR and D Flip-Flop 241
A Simple Strategy for Optimized Design of One-Level Carry-Skip Adders 239
"EChO" Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions 237
A Simple and Accurate Model of Input capacitance for Power Estimation in CMOS logic 236
Design Strategies for Source Coupled Logic Gates 231
Power-Delay Optimization of D-Latch/MUX Source Coupled Logic Gates 225
An Efficient Implementation of PRNGs Based on the Digital Sawtooth Map 225
Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study 223
An approach to the design of PFSCL gates 220
The Digital Tent Map: Performance Analysis and Optimized Design as a Source of Pseudo-Random Bits 220
Hardware-Efficient PRBGs Based on 1-D Piecewise Linear Chaotic Maps 218
A Design Methodology for High-Speed Low-Power MCML Frequency Dividers 217
Analysis and design of MCML gates with hysteresis 217
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies 216
The Digital Tent Map: Performance Analysis and Optimized Design as a Low Complexity Source of Pseudo-Random Bits 215
45pW ESD clamp circuit for ultra-low power applicationsProceedings of the IEEE 2013 Custom Integrated Circuits Conference 213
Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits from Experimental Measurements 212
Very Fast Carry Energy Efficient Computation based on Mixed Dynamic/Transmission-Gate Full Adders 211
Compact and Simple Output Transition Time Model in Nanometer CMOS Gates 211
NAND/NOR Adiabatic Gates: Power Consumption Evaluation and Comparison versus the Fan-In 208
Trading off static power and dynamic performance in CMOS digital circuits: bulk versus double gate SOI MOSFETs 202
Power Estimation in Adiabatic Circuits: A Simple and Accurate Model 202
Uniform-Distributed Noise Generator Based on a Chaotic Circuit 201
Power-aware design of nanometer MCML tapered buffers 200
Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I-Device-Circuit Interaction and Evaluation at Device Level 200
Design of Cascaded ECL Gates with a Power Constraint 199
Exploiting Hysteresys in MCML Circuits 197
Maximum-Period PRNGs Derived From A Piecewise Linear One-Dimensional Map 195
Design in the Energy-Delay Space 195
Positive-Feedback Source-Coupled Logic: a delay model 194
Impact of High-Mobility Materials on the Performance of Near- and Sub-Threshold CMOS Logic Circuits 194
Analysis and performance evaluation of area-efficient true random bit generators on FPGAs 191
Performance Evaluation of the Low-Voltage CML D-Latch Topology 188
Highly Accurate and Simple Models for CML and ECL gates 188
Mixed Techniques to Protect Precharged Busses against Differential Power Analysis Attacks 188
Analysis of Layout Density in FinFET Standard Cells and Impact of Fin Technology 187
Optimized Design of Parallel Carry-Select Adders 186
Metrics and Design Considerations on the Energy-Delay Tradeoff of Digital Circuits 186
Power-Aware Design Techniques for Nanometer MOS Current-Mode Logic Gates: a Design Framework 186
Tapered-Vth Approach for Energy-Efficient CMOS Buffers 185
Techniques to enhance the resistance of precharged busses to differential power analysis 185
Analysis and design of digital PRNGS based on the discretized sawtooth map 185
Power Analysis Attacks to Cryptographic Circuits: a Comparative Analysis of DPA and CPA 184
Nanometer Flip-Flops Design in the E-D Space 184
Closed-Form Analysis of DC Noise Immunity in Subthreshold CMOS Logic Circuits 184
Modeling strategies of the input admittance of RC interconnects for VLSI CAD tools 183
Understanding the effect of process variations on the delay of static and domino logic 183
Analysis and Modeling of Energy Consumption in RLC Tree Circuits 183
Understanding DC Behavior of Subthreshold CMOS Logic through Closed-Form Analysis 183
Optimized design of high fan-in multiplexers using tri-state buffers 182
Analysis of the impact of process variations on static logic circuits versus fan-in 182
Experimental Study of Leakage-Delay Trade-off in Germanium pMOSFETs for Logic Circuits 181
Comparative Evaluation of Layout Density in 3T, 4T and MT FinFET Standard Cells 180
Efficient Post-Processing Module for a Chaos-based Random Bit Generator 180
Design metrics for RTL level estimation of delay variability due to intradie (random) variations 179
Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison 179
Oscillation Frequency in CML and ESCL Ring Oscillators 178
Buried Silicon Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits under Aggressive Voltage Scaling 178
Leakage Power Analysis Attacks: Effectiveness on DPA Resistant Logic Styles under Process Variations 178
Leakage Power Analysis attacks against a bit slice implementation of the Serpent block cipher2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES) 178
Explicit Energy Evaluation in RLC Tree Circuits with Ramp Inputs 178
Delay Estimation of SCL Gates with Output Buffer 177
Leakage Power Analysis Attacks: Well-Defined Procedure and First Experimental Results 177
Analysis and Comparison on Full Adder Block in Sub-Micron Technology 177
Energy Consumption in RLC Tree Circuits 176
Long Period Pseudo Random Bit Generators Derived from a Discretized Chaotic Map 176
Simple and Accurate Modeling of the Output Transition Time in Nanometer CMOS Gates 175
Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency Dividers 174
Analysis and Design of Ultra-Low Power Subthreshold MCML Gates 174
Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects 174
Modeling and Evaluation of Positive-Feedback Source-Coupled Logic 174
Mixed FBB/RBB: a Novel Low-Leakage Technique for FinFET Forced Stacks 173
CML and ECL: Optimized Design and Comparison 172
Performance Evaluation of Adiabatic Gates 172
Adiabatic Gates: a Critical Point of View 171
Analysis and Evaluation of Layout Density of FinFET Logic Gates 171
Design of Low-Power High-Speed Bipolar Frequency Dividers 171
Impact of Clock Slope on Energy/Delay of Pulsed Flip-Flops and Optimum Clock Domain Design 169
Very High-Speed Carry Computation based on Mixed Dynamic/Transmission-Gate Full Adders 168
High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology 166
Flip-Flop Energy/Performance versus Clock Slope and Impact on the Clock Network Design 165
Correct Procedures to Evaluate the Effect of Intradie Variations on the Delay Variability of Digital Circuits 165
Design of MUX, XOR and D-Latch SCL gates 164
Totale 20.647
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Categoria #
all - tutte 87.019
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 87.019
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021651 0 0 0 0 0 0 0 0 0 190 286 175
2021/20221.834 164 296 112 65 90 109 102 55 82 249 159 351
2022/20232.727 179 156 350 426 250 584 55 209 263 131 78 46
2023/20241.305 80 39 93 125 40 360 441 16 7 21 13 70
2024/20253.370 85 198 202 166 370 169 56 239 192 134 379 1.180
2025/20266.850 666 1.338 914 684 1.123 277 877 223 243 505 0 0
Totale 29.747