IRIS
ALIOTO, MASSIMO BRUNO CRIS
 Distribuzione geografica
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Continente #
NA - Nord America 10.449
EU - Europa 7.805
AS - Asia 1.118
Continente sconosciuto - Info sul continente non disponibili 9
OC - Oceania 7
SA - Sud America 5
AF - Africa 4
Totale 19.397
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Nazione #
US - Stati Uniti d'America 10.439
GB - Regno Unito 2.344
DE - Germania 1.827
IE - Irlanda 1.057
CN - Cina 976
UA - Ucraina 942
SE - Svezia 508
FR - Francia 465
FI - Finlandia 211
IT - Italia 147
RU - Federazione Russa 126
ES - Italia 107
TR - Turchia 83
IN - India 21
BE - Belgio 19
NL - Olanda 13
CA - Canada 10
EU - Europa 9
RO - Romania 8
AU - Australia 6
EE - Estonia 6
HK - Hong Kong 6
AT - Austria 4
JP - Giappone 4
SG - Singapore 4
TW - Taiwan 4
BG - Bulgaria 3
BR - Brasile 3
CH - Svizzera 3
CY - Cipro 3
ID - Indonesia 3
IR - Iran 3
NG - Nigeria 3
PH - Filippine 3
IM - Isola di Man 2
IQ - Iraq 2
KR - Corea 2
PT - Portogallo 2
AE - Emirati Arabi Uniti 1
AR - Argentina 1
BN - Brunei Darussalam 1
CL - Cile 1
CZ - Repubblica Ceca 1
DK - Danimarca 1
EG - Egitto 1
GR - Grecia 1
HR - Croazia 1
HU - Ungheria 1
IL - Israele 1
LA - Repubblica Popolare Democratica del Laos 1
LI - Liechtenstein 1
LU - Lussemburgo 1
LV - Lettonia 1
MC - Monaco 1
MD - Moldavia 1
NZ - Nuova Zelanda 1
PL - Polonia 1
Totale 19.397
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Città #
Southend 2.199
Fairfield 1.929
Dublin 1.055
Houston 1.032
Woodbridge 924
Ashburn 883
Jacksonville 769
Seattle 749
Chandler 735
Wilmington 666
Cambridge 665
Ann Arbor 385
Princeton 316
Nanjing 276
Beijing 137
San Diego 118
Málaga 107
Boardman 94
Nanchang 92
Izmir 78
Shenyang 76
San Mateo 71
Hebei 51
Siena 50
Helsinki 49
Kunming 46
Jiaxing 40
Tianjin 38
Changsha 29
Shanghai 29
Mestre 28
London 27
Zhengzhou 26
Norwalk 23
Jinan 22
Dearborn 19
Hangzhou 19
Brussels 18
Ningbo 15
Guangzhou 14
Lanzhou 13
New York 12
Redwood City 12
Changchun 11
Tappahannock 11
Chicago 8
Florence 8
Toronto 8
Grünheide 7
Philadelphia 7
Rome 7
Dallas 6
Edinburgh 6
Hounslow 6
Indiana 6
New Bedfont 6
San Francisco 6
Taizhou 6
Tallinn 6
Amsterdam 5
Braunschweig 5
Bucharest 5
Buffalo 5
Fremont 5
Kilburn 5
Kocaeli 5
Dronten 4
Falls Church 4
Old Bridge 4
Prescot 4
Washington 4
Berlin 3
Brasov 3
Düsseldorf 3
Hefei 3
Lagos 3
Lancaster 3
Pune 3
Qingdao 3
Sofia 3
Stockholm 3
Strovolos 3
Turin 3
Vienna 3
Baghdad 2
Carson City 2
Catania 2
Central 2
Chengdu 2
Cividale Del Friuli 2
Concord 2
Fuzhou 2
Gelsenkirchen 2
Geneva 2
Grinzane Cavour 2
Hanover 2
Hosur 2
Hyderabad 2
Jinhua 2
Jundiaí 2
Totale 14.177
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Nome #
Mixed Full Adder Topologies for High-Performance Low-Power Arithmetic Circuits 352
Implementation Efficient Maximum-Period Nonlinear Congruential Generators 203
Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under Process Variations 185
“Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial 182
Exploiting Locality to Improve Leakage Reduction in Embedded Drowsy I-Caches at Same Area/Speed 181
Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study 179
Evaluation of Energy Consumption in RC Ladder Circuits Driven by a Ramp Input 176
Modeling and Optimized Design of Current Mode MUX/XOR and D Flip-Flop 175
A technique to design high entropy chaos-based true random bit generators 175
A Feedback Strategy to Improve the Entropy of a Chaos-Based Random Bit Generator 173
13.8 A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 167
Hardware-Efficient PRBGs Based on 1-D Piecewise Linear Chaotic Maps 164
Very Fast Carry Energy Efficient Computation based on Mixed Dynamic/Transmission-Gate Full Adders 157
A Simple Keeper Topology to Reduce Delay Variations in Nanometer Domino Logic 157
Trading off static power and dynamic performance in CMOS digital circuits: bulk versus double gate SOI MOSFETs 157
The Digital Tent Map: Performance Analysis and Optimized Design as a Source of Pseudo-Random Bits. 155
Analysis and performance evaluation of area-efficient true random bit generators on FPGAs 153
A scalable low-entropy detector to counteract the parameter variability effects in TRBGs 150
Design in the Energy-Delay Space 150
A variability-tolerant feedback technique for throughput maximization of TRBGs with predefined entropy 149
Uniform-Distributed Noise Generator Based on a Chaotic Circuit 149
Design Strategies for Source Coupled Logic Gates 148
A general model for differential power analysis attacks to static logic circuits 148
Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits from Experimental Measurements 146
Compact and Simple Output Transition Time Model in Nanometer CMOS Gates 146
Maximum-Period PRNGs Derived From A Piecewise Linear One-Dimensional Map 145
Analysis and design of MCML gates with hysteresis 145
Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I-Device-Circuit Interaction and Evaluation at Device Level 144
Leakage Power Analysis attacks against a bit slice implementation of the Serpent block cipher2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES) 144
The Digital Tent Map: Performance Analysis and Optimized Design as a Low Complexity Source of Pseudo-Random Bits 142
Power-Delay Optimization of D-Latch/MUX Source Coupled Logic Gates 141
Impact of High-Mobility Materials on the Performance of Near- and Sub-Threshold CMOS Logic Circuits 138
A Simple and Accurate Model of Input capacitance for Power Estimation in CMOS logic 137
Optimized Design of Parallel Carry-Select Adders 137
A Simple Strategy for Optimized Design of One-Level Carry-Skip Adders 136
A Novel Back-Biasing Low-Leakage Technique for FinFET Forced Stacks 135
Highly Accurate and Simple Models for CML and ECL gates 134
Long Period Pseudo Random Bit Generators Derived from a Discretized Chaotic Map 134
Techniques to enhance the resistance of precharged busses to differential power analysis 133
Power Estimation in Adiabatic Circuits: A Simple and Accurate Model 133
"EChO" Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions 133
Design of Cascaded ECL Gates with a Power Constraint 132
A general power model of Differential Power Analysis attacks to static logic circuits 131
Leakage Power Analysis Attacks: Effectiveness on DPA Resistant Logic Styles under Process Variations 131
Tapered-Vth Approach for Energy-Efficient CMOS Buffers 130
Design metrics for RTL level estimation of delay variability due to intradie (random) variations 130
NAND/NOR Adiabatic Gates: Power Consumption Evaluation and Comparison versus the Fan-In 129
Buried Silicon Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits under Aggressive Voltage Scaling 129
Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison 129
Explicit Energy Evaluation in RLC Tree Circuits with Ramp Inputs 129
Mixed FBB/RBB: a Novel Low-Leakage Technique for FinFET Forced Stacks 128
Efficient Post-Processing Module for a Chaos-based Random Bit Generator 128
Power-aware design of nanometer MCML tapered buffers 126
Understanding the effect of process variations on the delay of static and domino logic 126
Analysis and Modeling of Energy Consumption in RLC Tree Circuits 126
Very High-Speed Carry Computation based on Mixed Dynamic/Transmission-Gate Full Adders 126
A Design Methodology for High-Speed Low-Power MCML Frequency Dividers 125
Experimental Study of Leakage-Delay Trade-off in Germanium pMOSFETs for Logic Circuits 125
Analysis and Comparison on Full Adder Block in Sub-Micron Technology 125
Analysis and design of digital PRNGS based on the discretized sawtooth map 124
Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects 123
Low-Standby Current 4T FinFET Buffers: Analysis and Evaluation below 45 nm 123
Comparative Evaluation of Layout Density in 3T, 4T and MT FinFET Standard Cells 122
Nanometer Flip-Flops Design in the E-D Space 122
Closed-Form Analysis of DC Noise Immunity in Subthreshold CMOS Logic Circuits 122
Optimization of the Wire Grid Size for Differential Routing: Analysis and Impact on the Power-Delay-Area Tradeoff 122
Exploiting Hysteresys in MCML Circuits 121
Understanding DC Behavior of Subthreshold CMOS Logic through Closed-Form Analysis 121
Analysis of Layout Density in FinFET Standard Cells and Impact of Fin Technology 120
Improving the Power-Delay Product in SCL Circuits Using Source Follower Output Stage 120
An Efficient Implementation of PRNGs Based on the Digital Sawtooth Map. 120
Positive-Feedback Source-Coupled Logic: a delay model 120
Delay Estimation of SCL Gates with Output Buffer 119
Mixed Techniques to Protect Precharged Busses against Differential Power Analysis Attacks 119
Design of Low-Power High-Speed Bipolar Frequency Dividers 119
Optimized design of high fan-in multiplexers using tri-state buffers 118
Oscillation Frequency in CML and ESCL Ring Oscillators 118
Metrics and Design Considerations on the Energy-Delay Tradeoff of Digital Circuits 118
Simple and Accurate Modeling of the Output Transition Time in Nanometer CMOS Gates 118
Leakage Power Analysis Attacks: Well-Defined Procedure and First Experimental Results 118
Modeling and Evaluation of Positive-Feedback Source-Coupled Logic 118
CML and ECL: Optimized Design and Comparison 117
Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency Dividers 117
Power Analysis Attacks to Cryptographic Circuits: a Comparative Analysis of DPA and CPA 117
Performance Evaluation of Adiabatic Gates 117
Analysis of the impact of process variations on static logic circuits versus fan-in 115
Flip-Flop Energy/Performance versus Clock Slope and Impact on the Clock Network Design 115
Modeling strategies of the input admittance of RC interconnects for VLSI CAD tools 115
An approach to the design of PFSCL gates 115
Analysis and Evaluation of Layout Density of FinFET Logic Gates 115
Performance Evaluation of the Low-Voltage CML D-Latch Topology 114
Energy Consumption in RLC Tree Circuits 114
A general model of DPA attacks to precharged busses in symmetric-key cryptographic algorithms 114
Analysis and Design of Ultra-Low Power Subthreshold MCML Gates 114
Clock Distribution in Clock Domains with Dual-Edge-Triggered Flip-Flops to improve Energy-Efficiency 114
Tapered-VTH CMOS Buffer Design for Improved Energy Efficiency in Deep Nanometer Technology 113
Correct Procedures to Evaluate the Effect of Intradie Variations on the Delay Variability of Digital Circuits 112
Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits 111
A Class of Maximum-Period Nonlinear Congruential Generators Derived From the Rényi Chaotic Map 109
Design strategies of Cascaded CML Gates 109
Totale 13.605
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Categoria #
all - tutte 53.920
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 53.920
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2018/20192.080 0 0 0 0 0 0 0 0 0 493 845 742
2019/20205.187 593 320 333 880 438 420 373 692 413 368 79 278
2020/20213.710 298 373 212 426 157 380 240 499 474 190 286 175
2021/20221.834 164 296 112 65 90 109 102 55 82 249 159 351
2022/20232.727 179 156 350 426 250 584 55 209 263 131 78 46
2023/20241.221 80 39 93 125 40 360 441 16 7 20 0 0
Totale 19.443