IRIS
ALIOTO, MASSIMO BRUNO CRIS
 Distribuzione geografica
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Continente #
NA - Nord America 15.650
EU - Europa 10.269
AS - Asia 5.356
SA - Sud America 958
AF - Africa 169
Continente sconosciuto - Info sul continente non disponibili 55
OC - Oceania 9
AN - Antartide 1
Totale 32.467
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Nazione #
US - Stati Uniti d'America 15.478
GB - Regno Unito 2.426
CN - Cina 2.057
DE - Germania 1.891
SG - Singapore 1.472
RU - Federazione Russa 1.338
IE - Irlanda 1.064
UA - Ucraina 949
IT - Italia 924
BR - Brasile 805
FR - Francia 638
SE - Svezia 523
HK - Hong Kong 483
VN - Vietnam 436
KR - Corea 300
FI - Finlandia 226
IN - India 160
ES - Italia 122
TR - Turchia 105
CA - Canada 93
BD - Bangladesh 68
AR - Argentina 67
NG - Nigeria 54
IQ - Iraq 48
ZA - Sudafrica 42
MX - Messico 37
PL - Polonia 32
JP - Giappone 27
ID - Indonesia 25
NL - Olanda 24
BE - Belgio 22
PK - Pakistan 22
MA - Marocco 17
VE - Venezuela 17
CL - Cile 15
EC - Ecuador 15
EG - Egitto 15
SA - Arabia Saudita 15
UZ - Uzbekistan 15
PY - Paraguay 14
AT - Austria 11
CO - Colombia 11
NP - Nepal 11
RO - Romania 11
AZ - Azerbaigian 10
IR - Iran 10
PH - Filippine 10
CZ - Repubblica Ceca 9
EU - Europa 9
JO - Giordania 9
TN - Tunisia 9
AE - Emirati Arabi Uniti 8
AU - Australia 8
PE - Perù 8
TW - Taiwan 8
BG - Bulgaria 7
CH - Svizzera 7
GR - Grecia 7
JM - Giamaica 7
KE - Kenya 7
LT - Lituania 7
CR - Costa Rica 6
EE - Estonia 6
MY - Malesia 6
CY - Cipro 5
DZ - Algeria 5
IL - Israele 5
KZ - Kazakistan 5
TH - Thailandia 5
AM - Armenia 4
BB - Barbados 4
BH - Bahrain 4
CI - Costa d'Avorio 4
DO - Repubblica Dominicana 4
HN - Honduras 4
OM - Oman 4
PT - Portogallo 4
RS - Serbia 4
TT - Trinidad e Tobago 4
UY - Uruguay 4
QA - Qatar 3
AL - Albania 2
AO - Angola 2
BS - Bahamas 2
ET - Etiopia 2
GA - Gabon 2
GT - Guatemala 2
HU - Ungheria 2
IM - Isola di Man 2
KG - Kirghizistan 2
KN - Saint Kitts e Nevis 2
LA - Repubblica Popolare Democratica del Laos 2
LB - Libano 2
LK - Sri Lanka 2
MD - Moldavia 2
NI - Nicaragua 2
SN - Senegal 2
SY - Repubblica araba siriana 2
TZ - Tanzania 2
AQ - Antartide 1
Totale 32.392
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Città #
Southend 2.199
Fairfield 1.932
Ashburn 1.385
Dallas 1.355
Dublin 1.062
Houston 1.059
Woodbridge 925
Jacksonville 776
Seattle 767
Singapore 745
Chandler 735
Wilmington 667
Cambridge 665
Santa Clara 529
Hong Kong 461
Milan 408
Ann Arbor 385
Beijing 382
Hefei 326
Princeton 317
Moscow 299
Seoul 295
Nanjing 277
The Dalles 252
Los Angeles 202
Council Bluffs 186
San Jose 178
Ho Chi Minh City 143
Rome 142
Lauterbourg 141
Hanoi 127
San Diego 120
New York 109
Málaga 107
Boardman 98
Nanchang 92
Buffalo 80
Izmir 79
Shenyang 77
San Mateo 71
Helsinki 59
Columbus 53
Hebei 51
São Paulo 51
Abuja 50
Figino 50
London 50
Siena 50
Kunming 46
Bengaluru 43
Shanghai 42
Tianjin 42
Chicago 40
Jiaxing 40
Orem 40
San Francisco 40
Denver 39
Brooklyn 38
Atlanta 34
Changsha 34
Guangzhou 29
Johannesburg 29
Mestre 28
Toronto 27
Zhengzhou 27
Haiphong 26
Redondo Beach 26
Frankfurt am Main 25
Turin 25
Warsaw 25
Norwalk 24
Phoenix 23
Chennai 22
Jinan 22
Montreal 22
Hangzhou 21
Dearborn 20
Belo Horizonte 19
Boston 18
Brussels 18
Tokyo 18
Baghdad 17
Da Nang 17
Philadelphia 17
Rio de Janeiro 17
Munich 16
Ningbo 16
Stockholm 16
Lanzhou 15
Manchester 15
Changchun 14
Florence 14
Porto Alegre 13
New Delhi 12
Redwood City 12
Tashkent 12
Bari 11
Curitiba 11
Tappahannock 11
Baku 10
Totale 21.807
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Nome #
"EChO" Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions 1.322
Mixed Full Adder Topologies for High-Performance Low-Power Arithmetic Circuits 469
A Feedback Strategy to Improve the Entropy of a Chaos-Based Random Bit Generator 362
Adiabatic Gates: a Critical Point of View 334
A Class of Maximum-Period Nonlinear Congruential Generators Derived From the Rényi Chaotic Map 315
Evaluation of Energy Consumption in RC Ladder Circuits Driven by a Ramp Input 289
A scalable low-entropy detector to counteract the parameter variability effects in TRBGs 285
A technique to design high entropy chaos-based true random bit generators 278
A general power model of Differential Power Analysis attacks to static logic circuits 274
13.8 A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 273
Implementation Efficient Maximum-Period Nonlinear Congruential Generators 269
Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial 269
A general model of DPA attacks to precharged busses in symmetric-key cryptographic algorithms 268
A general model for differential power analysis attacks to static logic circuits 267
A Simple Keeper Topology to Reduce Delay Variations in Nanometer Domino Logic 261
A Novel Back-Biasing Low-Leakage Technique for FinFET Forced Stacks 260
Exploiting Locality to Improve Leakage Reduction in Embedded Drowsy I-Caches at Same Area/Speed 258
A variability-tolerant feedback technique for throughput maximization of TRBGs with predefined entropy 256
Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under Process Variations 254
A Simple Strategy for Optimized Design of One-Level Carry-Skip Adders 253
Modeling and Optimized Design of Current Mode MUX/XOR and D Flip-Flop 252
A Simple and Accurate Model of Input capacitance for Power Estimation in CMOS logic 243
Power-Delay Optimization of D-Latch/MUX Source Coupled Logic Gates 240
Design Strategies for Source Coupled Logic Gates 240
A Design Methodology for High-Speed Low-Power MCML Frequency Dividers 236
An approach to the design of PFSCL gates 233
The Digital Tent Map: Performance Analysis and Optimized Design as a Source of Pseudo-Random Bits 231
An Efficient Implementation of PRNGs Based on the Digital Sawtooth Map 230
Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study 227
Hardware-Efficient PRBGs Based on 1-D Piecewise Linear Chaotic Maps 226
The Digital Tent Map: Performance Analysis and Optimized Design as a Low Complexity Source of Pseudo-Random Bits 224
Analysis and design of MCML gates with hysteresis 224
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies 222
NAND/NOR Adiabatic Gates: Power Consumption Evaluation and Comparison versus the Fan-In 220
Very Fast Carry Energy Efficient Computation based on Mixed Dynamic/Transmission-Gate Full Adders 218
Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits from Experimental Measurements 218
Compact and Simple Output Transition Time Model in Nanometer CMOS Gates 217
45pW ESD clamp circuit for ultra-low power applicationsProceedings of the IEEE 2013 Custom Integrated Circuits Conference 216
Exploiting Hysteresys in MCML Circuits 213
Power Estimation in Adiabatic Circuits: A Simple and Accurate Model 213
Trading off static power and dynamic performance in CMOS digital circuits: bulk versus double gate SOI MOSFETs 211
Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I-Device-Circuit Interaction and Evaluation at Device Level 210
Power-aware design of nanometer MCML tapered buffers 209
Uniform-Distributed Noise Generator Based on a Chaotic Circuit 208
Maximum-Period PRNGs Derived From A Piecewise Linear One-Dimensional Map 206
Mixed Techniques to Protect Precharged Busses against Differential Power Analysis Attacks 204
Design in the Energy-Delay Space 203
Understanding the effect of process variations on the delay of static and domino logic 203
Design of Cascaded ECL Gates with a Power Constraint 202
Power-Aware Design Techniques for Nanometer MOS Current-Mode Logic Gates: a Design Framework 202
Analysis and performance evaluation of area-efficient true random bit generators on FPGAs 201
Performance Evaluation of the Low-Voltage CML D-Latch Topology 199
Analysis of Layout Density in FinFET Standard Cells and Impact of Fin Technology 199
Positive-Feedback Source-Coupled Logic: a delay model 199
Impact of High-Mobility Materials on the Performance of Near- and Sub-Threshold CMOS Logic Circuits 199
Highly Accurate and Simple Models for CML and ECL gates 198
Metrics and Design Considerations on the Energy-Delay Tradeoff of Digital Circuits 197
Analysis and design of digital PRNGS based on the discretized sawtooth map 196
Power Analysis Attacks to Cryptographic Circuits: a Comparative Analysis of DPA and CPA 195
Closed-Form Analysis of DC Noise Immunity in Subthreshold CMOS Logic Circuits 194
Explicit Energy Evaluation in RLC Tree Circuits with Ramp Inputs 194
Techniques to enhance the resistance of precharged busses to differential power analysis 193
Analysis and Comparison on Full Adder Block in Sub-Micron Technology 193
Experimental Study of Leakage-Delay Trade-off in Germanium pMOSFETs for Logic Circuits 192
Optimized Design of Parallel Carry-Select Adders 192
Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison 192
Oscillation Frequency in CML and ESCL Ring Oscillators 191
Comparative Evaluation of Layout Density in 3T, 4T and MT FinFET Standard Cells 191
Analysis and Design of Ultra-Low Power Subthreshold MCML Gates 191
Optimized design of high fan-in multiplexers using tri-state buffers 190
Nanometer Flip-Flops Design in the E-D Space 189
Tapered-Vth Approach for Energy-Efficient CMOS Buffers 189
Analysis and Modeling of Energy Consumption in RLC Tree Circuits 189
Understanding DC Behavior of Subthreshold CMOS Logic through Closed-Form Analysis 189
Efficient Post-Processing Module for a Chaos-based Random Bit Generator 189
Analysis of the impact of process variations on static logic circuits versus fan-in 188
Mixed FBB/RBB: a Novel Low-Leakage Technique for FinFET Forced Stacks 188
Energy Consumption in RLC Tree Circuits 187
Analysis and Evaluation of Layout Density of FinFET Logic Gates 187
Leakage Power Analysis Attacks: Effectiveness on DPA Resistant Logic Styles under Process Variations 187
Leakage Power Analysis Attacks: Well-Defined Procedure and First Experimental Results 187
Long Period Pseudo Random Bit Generators Derived from a Discretized Chaotic Map 186
Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency Dividers 184
Delay Estimation of SCL Gates with Output Buffer 184
Modeling strategies of the input admittance of RC interconnects for VLSI CAD tools 184
Design metrics for RTL level estimation of delay variability due to intradie (random) variations 184
Leakage Power Analysis attacks against a bit slice implementation of the Serpent block cipher2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES) 184
Simple and Accurate Modeling of the Output Transition Time in Nanometer CMOS Gates 183
Impact of Clock Slope on Energy/Delay of Pulsed Flip-Flops and Optimum Clock Domain Design 182
Buried Silicon Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits under Aggressive Voltage Scaling 182
Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects 182
Design of Low-Power High-Speed Bipolar Frequency Dividers 180
Performance Evaluation of Adiabatic Gates 179
Modeling and Evaluation of Positive-Feedback Source-Coupled Logic 179
CML and ECL: Optimized Design and Comparison 178
Flip-Flop Energy/Performance versus Clock Slope and Impact on the Clock Network Design 178
Very High-Speed Carry Computation based on Mixed Dynamic/Transmission-Gate Full Adders 177
Correct Procedures to Evaluate the Effect of Intradie Variations on the Delay Variability of Digital Circuits 176
High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology 174
Design of MUX, XOR and D-Latch SCL gates 173
Totale 22.811
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Categoria #
all - tutte 94.528
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 94.528
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2021/20221.670 0 296 112 65 90 109 102 55 82 249 159 351
2022/20232.727 179 156 350 426 250 584 55 209 263 131 78 46
2023/20241.305 80 39 93 125 40 360 441 16 7 21 13 70
2024/20253.370 85 198 202 166 370 169 56 239 192 134 379 1.180
2025/20268.869 666 1.338 914 684 1.123 277 877 223 243 526 1.176 822
2026/2027701 488 213 0 0 0 0 0 0 0 0 0 0
Totale 32.467