IRIS
ALIOTO, MASSIMO BRUNO CRIS
 Distribuzione geografica
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Continente #
NA - Nord America 10.975
EU - Europa 8.291
AS - Asia 1.403
SA - Sud America 26
Continente sconosciuto - Info sul continente non disponibili 9
OC - Oceania 8
AF - Africa 7
Totale 20.719
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Nazione #
US - Stati Uniti d'America 10.958
GB - Regno Unito 2.349
DE - Germania 1.833
IE - Irlanda 1.058
CN - Cina 1.032
UA - Ucraina 942
RU - Federazione Russa 579
SE - Svezia 508
FR - Francia 466
FI - Finlandia 216
SG - Singapore 210
IT - Italia 151
ES - Italia 107
TR - Turchia 83
IN - India 27
BR - Brasile 23
BE - Belgio 19
CA - Canada 17
NL - Olanda 15
HK - Hong Kong 11
EU - Europa 9
RO - Romania 8
TW - Taiwan 8
AU - Australia 7
CZ - Repubblica Ceca 7
EE - Estonia 6
AT - Austria 4
ID - Indonesia 4
JP - Giappone 4
KR - Corea 4
BG - Bulgaria 3
CH - Svizzera 3
CI - Costa d'Avorio 3
CY - Cipro 3
IR - Iran 3
LT - Lituania 3
NG - Nigeria 3
PH - Filippine 3
AM - Armenia 2
CL - Cile 2
IM - Isola di Man 2
IQ - Iraq 2
PT - Portogallo 2
AE - Emirati Arabi Uniti 1
AR - Argentina 1
BD - Bangladesh 1
BN - Brunei Darussalam 1
DK - Danimarca 1
EG - Egitto 1
GR - Grecia 1
HR - Croazia 1
HU - Ungheria 1
IL - Israele 1
LA - Repubblica Popolare Democratica del Laos 1
LI - Liechtenstein 1
LU - Lussemburgo 1
LV - Lettonia 1
MC - Monaco 1
MD - Moldavia 1
MY - Malesia 1
NP - Nepal 1
NZ - Nuova Zelanda 1
PL - Polonia 1
Totale 20.719
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Città #
Southend 2.199
Fairfield 1.929
Dublin 1.056
Houston 1.032
Woodbridge 924
Ashburn 886
Jacksonville 769
Seattle 756
Chandler 735
Wilmington 666
Cambridge 665
Santa Clara 431
Ann Arbor 385
Princeton 316
Nanjing 277
Beijing 140
San Diego 118
Singapore 115
Málaga 107
Boardman 98
Nanchang 92
Izmir 78
Shenyang 76
San Mateo 71
Helsinki 54
Hebei 51
Moscow 50
Siena 50
Kunming 46
Jiaxing 40
Tianjin 39
Shanghai 32
Changsha 30
London 30
Mestre 28
Zhengzhou 26
New York 24
Norwalk 23
Jinan 22
Dearborn 19
Hangzhou 19
Brussels 18
Guangzhou 17
Ningbo 16
Lanzhou 13
Redwood City 12
Changchun 11
Tappahannock 11
Toronto 11
Chicago 8
Florence 8
Dallas 7
Grünheide 7
Philadelphia 7
Rome 7
Edinburgh 6
Hounslow 6
Indiana 6
New Bedfont 6
San Francisco 6
Taizhou 6
Tallinn 6
Amsterdam 5
Braunschweig 5
Bucharest 5
Buffalo 5
Fremont 5
Hong Kong 5
Kilburn 5
Kocaeli 5
Piscataway 5
Bengaluru 4
Dronten 4
Falls Church 4
New Delhi 4
North Bergen 4
Old Bridge 4
Ottawa 4
Prague 4
Prescot 4
Washington 4
Abidjan 3
Berlin 3
Brasov 3
Chengdu 3
Düsseldorf 3
Hefei 3
Lagos 3
Lancaster 3
Pune 3
Qingdao 3
Sofia 3
Stockholm 3
Strovolos 3
Turin 3
Vienna 3
Baghdad 2
Carrara 2
Carson City 2
Catania 2
Totale 14.837
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Nome #
Mixed Full Adder Topologies for High-Performance Low-Power Arithmetic Circuits 388
Implementation Efficient Maximum-Period Nonlinear Congruential Generators 213
Evaluation of Energy Consumption in RC Ladder Circuits Driven by a Ramp Input 202
“Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial 197
Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under Process Variations 193
Exploiting Locality to Improve Leakage Reduction in Embedded Drowsy I-Caches at Same Area/Speed 192
A Feedback Strategy to Improve the Entropy of a Chaos-Based Random Bit Generator 190
A technique to design high entropy chaos-based true random bit generators 188
Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study 187
Modeling and Optimized Design of Current Mode MUX/XOR and D Flip-Flop 184
13.8 A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 183
Hardware-Efficient PRBGs Based on 1-D Piecewise Linear Chaotic Maps 173
The Digital Tent Map: Performance Analysis and Optimized Design as a Source of Pseudo-Random Bits 171
A Simple Keeper Topology to Reduce Delay Variations in Nanometer Domino Logic 168
A scalable low-entropy detector to counteract the parameter variability effects in TRBGs 167
Very Fast Carry Energy Efficient Computation based on Mixed Dynamic/Transmission-Gate Full Adders 165
Trading off static power and dynamic performance in CMOS digital circuits: bulk versus double gate SOI MOSFETs 165
A variability-tolerant feedback technique for throughput maximization of TRBGs with predefined entropy 164
Analysis and performance evaluation of area-efficient true random bit generators on FPGAs 161
Design Strategies for Source Coupled Logic Gates 160
A general model for differential power analysis attacks to static logic circuits 160
Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits from Experimental Measurements 156
Uniform-Distributed Noise Generator Based on a Chaotic Circuit 156
Design in the Energy-Delay Space 156
Compact and Simple Output Transition Time Model in Nanometer CMOS Gates 155
Analysis and design of MCML gates with hysteresis 155
Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I-Device-Circuit Interaction and Evaluation at Device Level 153
Power-Delay Optimization of D-Latch/MUX Source Coupled Logic Gates 152
Leakage Power Analysis attacks against a bit slice implementation of the Serpent block cipher2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES) 152
The Digital Tent Map: Performance Analysis and Optimized Design as a Low Complexity Source of Pseudo-Random Bits 151
Maximum-Period PRNGs Derived From A Piecewise Linear One-Dimensional Map 151
A Simple and Accurate Model of Input capacitance for Power Estimation in CMOS logic 149
A Simple Strategy for Optimized Design of One-Level Carry-Skip Adders 147
Optimized Design of Parallel Carry-Select Adders 147
Impact of High-Mobility Materials on the Performance of Near- and Sub-Threshold CMOS Logic Circuits 147
A Novel Back-Biasing Low-Leakage Technique for FinFET Forced Stacks 146
A general power model of Differential Power Analysis attacks to static logic circuits 145
Highly Accurate and Simple Models for CML and ECL gates 143
Techniques to enhance the resistance of precharged busses to differential power analysis 143
Long Period Pseudo Random Bit Generators Derived from a Discretized Chaotic Map 143
"EChO" Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions 143
Power Estimation in Adiabatic Circuits: A Simple and Accurate Model 141
Power-aware design of nanometer MCML tapered buffers 140
Design of Cascaded ECL Gates with a Power Constraint 140
Leakage Power Analysis Attacks: Effectiveness on DPA Resistant Logic Styles under Process Variations 140
Understanding the effect of process variations on the delay of static and domino logic 139
NAND/NOR Adiabatic Gates: Power Consumption Evaluation and Comparison versus the Fan-In 138
Design metrics for RTL level estimation of delay variability due to intradie (random) variations 138
Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison 138
Explicit Energy Evaluation in RLC Tree Circuits with Ramp Inputs 137
Efficient Post-Processing Module for a Chaos-based Random Bit Generator 137
Tapered-Vth Approach for Energy-Efficient CMOS Buffers 136
Buried Silicon Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits under Aggressive Voltage Scaling 136
Mixed FBB/RBB: a Novel Low-Leakage Technique for FinFET Forced Stacks 136
Analysis and Comparison on Full Adder Block in Sub-Micron Technology 135
Analysis and Modeling of Energy Consumption in RLC Tree Circuits 135
Very High-Speed Carry Computation based on Mixed Dynamic/Transmission-Gate Full Adders 135
A Design Methodology for High-Speed Low-Power MCML Frequency Dividers 134
Experimental Study of Leakage-Delay Trade-off in Germanium pMOSFETs for Logic Circuits 133
An Efficient Implementation of PRNGs Based on the Digital Sawtooth Map 132
Leakage Power Analysis Attacks: Well-Defined Procedure and First Experimental Results 132
Low-Standby Current 4T FinFET Buffers: Analysis and Evaluation below 45 nm 132
Comparative Evaluation of Layout Density in 3T, 4T and MT FinFET Standard Cells 131
A Class of Maximum-Period Nonlinear Congruential Generators Derived From the Rényi Chaotic Map 131
Analysis and design of digital PRNGS based on the discretized sawtooth map 131
Understanding DC Behavior of Subthreshold CMOS Logic through Closed-Form Analysis 131
Exploiting Hysteresys in MCML Circuits 130
Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects 130
Optimization of the Wire Grid Size for Differential Routing: Analysis and Impact on the Power-Delay-Area Tradeoff 130
Nanometer Flip-Flops Design in the E-D Space 129
Closed-Form Analysis of DC Noise Immunity in Subthreshold CMOS Logic Circuits 129
Optimized design of high fan-in multiplexers using tri-state buffers 128
A general model of DPA attacks to precharged busses in symmetric-key cryptographic algorithms 128
Analysis of Layout Density in FinFET Standard Cells and Impact of Fin Technology 128
Improving the Power-Delay Product in SCL Circuits Using Source Follower Output Stage 128
Mixed Techniques to Protect Precharged Busses against Differential Power Analysis Attacks 128
Positive-Feedback Source-Coupled Logic: a delay model 128
Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency Dividers 127
Delay Estimation of SCL Gates with Output Buffer 127
Simple and Accurate Modeling of the Output Transition Time in Nanometer CMOS Gates 127
Modeling and Evaluation of Positive-Feedback Source-Coupled Logic 127
Design of Low-Power High-Speed Bipolar Frequency Dividers 127
An approach to the design of PFSCL gates 126
CML and ECL: Optimized Design and Comparison 125
Oscillation Frequency in CML and ESCL Ring Oscillators 125
Power Analysis Attacks to Cryptographic Circuits: a Comparative Analysis of DPA and CPA 125
Modeling strategies of the input admittance of RC interconnects for VLSI CAD tools 125
Metrics and Design Considerations on the Energy-Delay Tradeoff of Digital Circuits 125
Performance Evaluation of Adiabatic Gates 124
Performance Evaluation of the Low-Voltage CML D-Latch Topology 123
Energy Consumption in RLC Tree Circuits 123
Analysis of the impact of process variations on static logic circuits versus fan-in 123
Flip-Flop Energy/Performance versus Clock Slope and Impact on the Clock Network Design 122
Analysis and Design of Ultra-Low Power Subthreshold MCML Gates 121
Tapered-VTH CMOS Buffer Design for Improved Energy Efficiency in Deep Nanometer Technology 121
Clock Distribution in Clock Domains with Dual-Edge-Triggered Flip-Flops to improve Energy-Efficiency 121
Design strategies of Cascaded CML Gates 121
Analysis and Evaluation of Layout Density of FinFET Logic Gates 120
45pW ESD clamp circuit for ultra-low power applicationsProceedings of the IEEE 2013 Custom Integrated Circuits Conference 120
Correct Procedures to Evaluate the Effect of Intradie Variations on the Delay Variability of Digital Circuits 118
Totale 14.608
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Categoria #
all - tutte 63.498
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 63.498
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20202.203 0 0 0 0 0 0 373 692 413 368 79 278
2020/20213.710 298 373 212 426 157 380 240 499 474 190 286 175
2021/20221.834 164 296 112 65 90 109 102 55 82 249 159 351
2022/20232.727 179 156 350 426 250 584 55 209 263 131 78 46
2023/20241.305 80 39 93 125 40 360 441 16 7 21 13 70
2024/20251.238 85 198 202 166 370 169 48 0 0 0 0 0
Totale 20.765