IRIS
ALIOTO, MASSIMO BRUNO CRIS
 Distribuzione geografica
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Continente #
NA - Nord America 14.960
EU - Europa 9.526
AS - Asia 5.304
SA - Sud America 944
AF - Africa 169
Continente sconosciuto - Info sul continente non disponibili 9
OC - Oceania 9
AN - Antartide 1
Totale 30.922
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Nazione #
US - Stati Uniti d'America 14.803
GB - Regno Unito 2.426
CN - Cina 2.045
DE - Germania 1.889
SG - Singapore 1.455
RU - Federazione Russa 1.338
IE - Irlanda 1.064
UA - Ucraina 948
BR - Brasile 797
FR - Francia 637
SE - Svezia 523
HK - Hong Kong 480
VN - Vietnam 434
KR - Corea 299
FI - Finlandia 226
IT - Italia 191
IN - India 159
ES - Italia 120
TR - Turchia 104
CA - Canada 84
AR - Argentina 65
BD - Bangladesh 57
NG - Nigeria 54
IQ - Iraq 48
ZA - Sudafrica 42
MX - Messico 35
PL - Polonia 32
JP - Giappone 26
ID - Indonesia 24
NL - Olanda 24
BE - Belgio 22
PK - Pakistan 22
MA - Marocco 17
VE - Venezuela 16
CL - Cile 15
EG - Egitto 15
SA - Arabia Saudita 15
UZ - Uzbekistan 15
PY - Paraguay 14
EC - Ecuador 13
AT - Austria 11
RO - Romania 11
AZ - Azerbaigian 10
CO - Colombia 10
IR - Iran 10
NP - Nepal 10
PH - Filippine 10
EU - Europa 9
JO - Giordania 9
TN - Tunisia 9
AU - Australia 8
CZ - Repubblica Ceca 8
PE - Perù 8
TW - Taiwan 8
AE - Emirati Arabi Uniti 7
BG - Bulgaria 7
CH - Svizzera 7
GR - Grecia 7
KE - Kenya 7
EE - Estonia 6
LT - Lituania 6
MY - Malesia 6
CR - Costa Rica 5
CY - Cipro 5
DZ - Algeria 5
IL - Israele 5
JM - Giamaica 5
KZ - Kazakistan 5
TH - Thailandia 5
AM - Armenia 4
BB - Barbados 4
BH - Bahrain 4
CI - Costa d'Avorio 4
DO - Repubblica Dominicana 4
OM - Oman 4
PT - Portogallo 4
TT - Trinidad e Tobago 4
UY - Uruguay 4
HN - Honduras 3
QA - Qatar 3
RS - Serbia 3
AL - Albania 2
AO - Angola 2
BS - Bahamas 2
ET - Etiopia 2
GA - Gabon 2
GT - Guatemala 2
HU - Ungheria 2
IM - Isola di Man 2
KG - Kirghizistan 2
KN - Saint Kitts e Nevis 2
LA - Repubblica Popolare Democratica del Laos 2
LB - Libano 2
LK - Sri Lanka 2
MD - Moldavia 2
NI - Nicaragua 2
SN - Senegal 2
SY - Repubblica araba siriana 2
TZ - Tanzania 2
AQ - Antartide 1
Totale 30.894
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Città #
Southend 2.199
Fairfield 1.931
Dallas 1.346
Ashburn 1.266
Dublin 1.062
Houston 1.056
Woodbridge 925
Jacksonville 774
Seattle 764
Singapore 736
Chandler 735
Wilmington 667
Cambridge 665
Santa Clara 472
Hong Kong 458
Ann Arbor 385
Beijing 376
Hefei 326
Princeton 317
Moscow 299
Seoul 295
Nanjing 277
The Dalles 252
Los Angeles 199
San Jose 177
Ho Chi Minh City 141
Lauterbourg 141
Hanoi 127
San Diego 120
Málaga 107
Boardman 98
New York 96
Nanchang 92
Council Bluffs 84
Buffalo 80
Izmir 79
Shenyang 77
San Mateo 71
Helsinki 59
Hebei 51
São Paulo 51
Abuja 50
London 50
Siena 50
Kunming 46
Bengaluru 43
Tianjin 42
Jiaxing 40
Orem 40
San Francisco 40
Shanghai 40
Denver 39
Chicago 38
Brooklyn 35
Changsha 34
Columbus 31
Guangzhou 29
Johannesburg 29
Mestre 28
Atlanta 27
Zhengzhou 27
Haiphong 26
Redondo Beach 26
Frankfurt am Main 25
Toronto 25
Warsaw 25
Norwalk 23
Chennai 22
Jinan 22
Hangzhou 21
Montreal 21
Phoenix 21
Belo Horizonte 19
Dearborn 19
Brussels 18
Baghdad 17
Da Nang 17
Rio de Janeiro 17
Tokyo 17
Munich 16
Ningbo 16
Stockholm 16
Manchester 15
Changchun 14
Lanzhou 14
Philadelphia 14
Boston 13
Porto Alegre 13
New Delhi 12
Redwood City 12
Tashkent 12
Curitiba 11
Tappahannock 11
Baku 10
Brasília 10
Campinas 10
Charlotte 10
Dhaka 10
Mumbai 10
Rome 10
Totale 20.831
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Nome #
"EChO" Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions 1.287
Mixed Full Adder Topologies for High-Performance Low-Power Arithmetic Circuits 456
A Feedback Strategy to Improve the Entropy of a Chaos-Based Random Bit Generator 350
A Class of Maximum-Period Nonlinear Congruential Generators Derived From the Rényi Chaotic Map 307
Evaluation of Energy Consumption in RC Ladder Circuits Driven by a Ramp Input 274
A scalable low-entropy detector to counteract the parameter variability effects in TRBGs 273
A technique to design high entropy chaos-based true random bit generators 272
A general power model of Differential Power Analysis attacks to static logic circuits 270
A general model of DPA attacks to precharged busses in symmetric-key cryptographic algorithms 266
Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial 265
A general model for differential power analysis attacks to static logic circuits 264
Implementation Efficient Maximum-Period Nonlinear Congruential Generators 264
13.8 A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 263
Exploiting Locality to Improve Leakage Reduction in Embedded Drowsy I-Caches at Same Area/Speed 256
A Simple Keeper Topology to Reduce Delay Variations in Nanometer Domino Logic 254
A variability-tolerant feedback technique for throughput maximization of TRBGs with predefined entropy 253
A Novel Back-Biasing Low-Leakage Technique for FinFET Forced Stacks 253
Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under Process Variations 245
Modeling and Optimized Design of Current Mode MUX/XOR and D Flip-Flop 241
A Simple Strategy for Optimized Design of One-Level Carry-Skip Adders 240
A Simple and Accurate Model of Input capacitance for Power Estimation in CMOS logic 237
Design Strategies for Source Coupled Logic Gates 233
Power-Delay Optimization of D-Latch/MUX Source Coupled Logic Gates 227
An Efficient Implementation of PRNGs Based on the Digital Sawtooth Map 227
Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study 223
An approach to the design of PFSCL gates 222
The Digital Tent Map: Performance Analysis and Optimized Design as a Source of Pseudo-Random Bits 221
A Design Methodology for High-Speed Low-Power MCML Frequency Dividers 220
Hardware-Efficient PRBGs Based on 1-D Piecewise Linear Chaotic Maps 220
Analysis and design of MCML gates with hysteresis 219
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies 218
The Digital Tent Map: Performance Analysis and Optimized Design as a Low Complexity Source of Pseudo-Random Bits 217
Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits from Experimental Measurements 213
45pW ESD clamp circuit for ultra-low power applicationsProceedings of the IEEE 2013 Custom Integrated Circuits Conference 213
Very Fast Carry Energy Efficient Computation based on Mixed Dynamic/Transmission-Gate Full Adders 211
Compact and Simple Output Transition Time Model in Nanometer CMOS Gates 211
NAND/NOR Adiabatic Gates: Power Consumption Evaluation and Comparison versus the Fan-In 209
Trading off static power and dynamic performance in CMOS digital circuits: bulk versus double gate SOI MOSFETs 204
Power Estimation in Adiabatic Circuits: A Simple and Accurate Model 204
Uniform-Distributed Noise Generator Based on a Chaotic Circuit 202
Power-aware design of nanometer MCML tapered buffers 201
Exploiting Hysteresys in MCML Circuits 201
Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I-Device-Circuit Interaction and Evaluation at Device Level 201
Design of Cascaded ECL Gates with a Power Constraint 200
Positive-Feedback Source-Coupled Logic: a delay model 196
Impact of High-Mobility Materials on the Performance of Near- and Sub-Threshold CMOS Logic Circuits 196
Maximum-Period PRNGs Derived From A Piecewise Linear One-Dimensional Map 195
Design in the Energy-Delay Space 195
Analysis and performance evaluation of area-efficient true random bit generators on FPGAs 192
Performance Evaluation of the Low-Voltage CML D-Latch Topology 189
Analysis of Layout Density in FinFET Standard Cells and Impact of Fin Technology 189
Mixed Techniques to Protect Precharged Busses against Differential Power Analysis Attacks 189
Power-Aware Design Techniques for Nanometer MOS Current-Mode Logic Gates: a Design Framework 189
Highly Accurate and Simple Models for CML and ECL gates 188
Analysis and design of digital PRNGS based on the discretized sawtooth map 188
Optimized Design of Parallel Carry-Select Adders 186
Metrics and Design Considerations on the Energy-Delay Tradeoff of Digital Circuits 186
Power Analysis Attacks to Cryptographic Circuits: a Comparative Analysis of DPA and CPA 185
Tapered-Vth Approach for Energy-Efficient CMOS Buffers 185
Techniques to enhance the resistance of precharged busses to differential power analysis 185
Closed-Form Analysis of DC Noise Immunity in Subthreshold CMOS Logic Circuits 185
Understanding DC Behavior of Subthreshold CMOS Logic through Closed-Form Analysis 185
Nanometer Flip-Flops Design in the E-D Space 184
Understanding the effect of process variations on the delay of static and domino logic 184
Modeling strategies of the input admittance of RC interconnects for VLSI CAD tools 183
Analysis and Modeling of Energy Consumption in RLC Tree Circuits 183
Optimized design of high fan-in multiplexers using tri-state buffers 182
Analysis of the impact of process variations on static logic circuits versus fan-in 182
Energy Consumption in RLC Tree Circuits 181
Experimental Study of Leakage-Delay Trade-off in Germanium pMOSFETs for Logic Circuits 181
Analysis and Comparison on Full Adder Block in Sub-Micron Technology 181
Efficient Post-Processing Module for a Chaos-based Random Bit Generator 181
Oscillation Frequency in CML and ESCL Ring Oscillators 180
Comparative Evaluation of Layout Density in 3T, 4T and MT FinFET Standard Cells 180
Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison 180
Explicit Energy Evaluation in RLC Tree Circuits with Ramp Inputs 180
Buried Silicon Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits under Aggressive Voltage Scaling 179
Design metrics for RTL level estimation of delay variability due to intradie (random) variations 179
Leakage Power Analysis Attacks: Effectiveness on DPA Resistant Logic Styles under Process Variations 179
Leakage Power Analysis Attacks: Well-Defined Procedure and First Experimental Results 179
Leakage Power Analysis attacks against a bit slice implementation of the Serpent block cipher2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES) 178
Delay Estimation of SCL Gates with Output Buffer 177
Modeling and Evaluation of Positive-Feedback Source-Coupled Logic 176
Long Period Pseudo Random Bit Generators Derived from a Discretized Chaotic Map 176
Analysis and Design of Ultra-Low Power Subthreshold MCML Gates 175
Simple and Accurate Modeling of the Output Transition Time in Nanometer CMOS Gates 175
Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects 175
Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency Dividers 174
Mixed FBB/RBB: a Novel Low-Leakage Technique for FinFET Forced Stacks 174
CML and ECL: Optimized Design and Comparison 173
Design of Low-Power High-Speed Bipolar Frequency Dividers 173
Adiabatic Gates: a Critical Point of View 172
Performance Evaluation of Adiabatic Gates 172
Impact of Clock Slope on Energy/Delay of Pulsed Flip-Flops and Optimum Clock Domain Design 171
Analysis and Evaluation of Layout Density of FinFET Logic Gates 171
Very High-Speed Carry Computation based on Mixed Dynamic/Transmission-Gate Full Adders 171
High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology 168
Flip-Flop Energy/Performance versus Clock Slope and Impact on the Clock Network Design 167
Correct Procedures to Evaluate the Effect of Intradie Variations on the Delay Variability of Digital Circuits 166
Design of MUX, XOR and D-Latch SCL gates 164
Totale 21.816
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Categoria #
all - tutte 90.738
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 90.738
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021175 0 0 0 0 0 0 0 0 0 0 0 175
2021/20221.834 164 296 112 65 90 109 102 55 82 249 159 351
2022/20232.727 179 156 350 426 250 584 55 209 263 131 78 46
2023/20241.305 80 39 93 125 40 360 441 16 7 21 13 70
2024/20253.370 85 198 202 166 370 169 56 239 192 134 379 1.180
2025/20268.071 666 1.338 914 684 1.123 277 877 223 243 526 1.176 24
Totale 30.968