IRIS
ALIOTO, MASSIMO BRUNO CRIS
 Distribuzione geografica
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Continente #
NA - Nord America 11.404
EU - Europa 8.397
AS - Asia 2.846
SA - Sud America 535
AF - Africa 43
Continente sconosciuto - Info sul continente non disponibili 9
OC - Oceania 9
Totale 23.243
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Nazione #
US - Stati Uniti d'America 11.344
GB - Regno Unito 2.376
DE - Germania 1.850
CN - Cina 1.303
IE - Irlanda 1.059
UA - Ucraina 947
SG - Singapore 616
RU - Federazione Russa 592
SE - Svezia 510
BR - Brasile 494
FR - Francia 468
HK - Hong Kong 389
FI - Finlandia 221
KR - Corea 185
IT - Italia 155
ES - Italia 114
IN - India 96
TR - Turchia 94
CA - Canada 30
IQ - Iraq 23
BD - Bangladesh 22
VN - Vietnam 22
BE - Belgio 19
NL - Olanda 19
AR - Argentina 15
JP - Giappone 13
MX - Messico 12
ZA - Sudafrica 12
PK - Pakistan 10
EU - Europa 9
AU - Australia 8
MA - Marocco 8
RO - Romania 8
SA - Arabia Saudita 8
TW - Taiwan 8
VE - Venezuela 8
CZ - Repubblica Ceca 7
PL - Polonia 7
EE - Estonia 6
GR - Grecia 6
AZ - Azerbaigian 5
EC - Ecuador 5
LT - Lituania 5
NP - Nepal 5
PY - Paraguay 5
UZ - Uzbekistan 5
AT - Austria 4
BG - Bulgaria 4
CL - Cile 4
CY - Cipro 4
ID - Indonesia 4
IR - Iran 4
KE - Kenya 4
NG - Nigeria 4
AM - Armenia 3
BB - Barbados 3
CH - Svizzera 3
CI - Costa d'Avorio 3
DZ - Algeria 3
EG - Egitto 3
HN - Honduras 3
IL - Israele 3
PH - Filippine 3
PT - Portogallo 3
TN - Tunisia 3
AE - Emirati Arabi Uniti 2
AO - Angola 2
BH - Bahrain 2
CO - Colombia 2
CR - Costa Rica 2
GT - Guatemala 2
HU - Ungheria 2
IM - Isola di Man 2
JM - Giamaica 2
JO - Giordania 2
KZ - Kazakistan 2
MD - Moldavia 2
NI - Nicaragua 2
OM - Oman 2
PE - Perù 2
TH - Thailandia 2
TT - Trinidad e Tobago 2
AL - Albania 1
BN - Brunei Darussalam 1
DK - Danimarca 1
DO - Repubblica Dominicana 1
GE - Georgia 1
HR - Croazia 1
KG - Kirghizistan 1
KN - Saint Kitts e Nevis 1
LA - Repubblica Popolare Democratica del Laos 1
LB - Libano 1
LI - Liechtenstein 1
LK - Sri Lanka 1
LU - Lussemburgo 1
LV - Lettonia 1
MC - Monaco 1
MN - Mongolia 1
MY - Malesia 1
NZ - Nuova Zelanda 1
Totale 23.240
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Città #
Southend 2.199
Fairfield 1.930
Dublin 1.057
Houston 1.034
Woodbridge 924
Ashburn 890
Jacksonville 769
Seattle 758
Chandler 735
Wilmington 667
Cambridge 665
Santa Clara 437
Ann Arbor 385
Hong Kong 383
Princeton 316
Singapore 308
Beijing 292
Nanjing 277
Seoul 183
San Diego 119
Hefei 116
Málaga 107
Boardman 98
Nanchang 92
Izmir 79
Shenyang 76
Council Bluffs 72
San Mateo 71
Helsinki 54
Hebei 51
Moscow 51
Siena 50
Kunming 46
Bengaluru 43
Jiaxing 40
Tianjin 39
London 32
Shanghai 32
The Dalles 32
Changsha 30
New York 30
Columbus 28
Mestre 28
Zhengzhou 26
Norwalk 23
Jinan 22
São Paulo 22
Dearborn 19
Hangzhou 19
Brussels 18
Guangzhou 17
Ningbo 16
Belo Horizonte 15
Munich 15
Toronto 15
Rio de Janeiro 14
Chicago 13
Lanzhou 13
Ho Chi Minh City 12
Redwood City 12
Changchun 11
San Francisco 11
Tappahannock 11
Baghdad 10
Curitiba 10
Dallas 10
Philadelphia 10
Los Angeles 9
New Delhi 9
Porto Alegre 9
Brooklyn 8
Campinas 8
Florence 8
Grünheide 7
Rome 7
Brasília 6
Buffalo 6
Edinburgh 6
Guarulhos 6
Hounslow 6
Indiana 6
Johannesburg 6
Jundiaí 6
New Bedfont 6
Newark 6
Piscataway 6
Ribeirão Preto 6
Taizhou 6
Tallinn 6
Warsaw 6
Amsterdam 5
Baku 5
Braunschweig 5
Bucharest 5
Fremont 5
Hanoi 5
Kilburn 5
Kocaeli 5
Recife 5
Santo André 5
Totale 16.194
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Nome #
Mixed Full Adder Topologies for High-Performance Low-Power Arithmetic Circuits 404
Implementation Efficient Maximum-Period Nonlinear Congruential Generators 233
Evaluation of Energy Consumption in RC Ladder Circuits Driven by a Ramp Input 221
A Feedback Strategy to Improve the Entropy of a Chaos-Based Random Bit Generator 217
Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial 217
Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under Process Variations 210
Exploiting Locality to Improve Leakage Reduction in Embedded Drowsy I-Caches at Same Area/Speed 203
A technique to design high entropy chaos-based true random bit generators 202
Modeling and Optimized Design of Current Mode MUX/XOR and D Flip-Flop 200
13.8 A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 200
Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study 195
Design Strategies for Source Coupled Logic Gates 192
The Digital Tent Map: Performance Analysis and Optimized Design as a Source of Pseudo-Random Bits 190
A scalable low-entropy detector to counteract the parameter variability effects in TRBGs 187
Very Fast Carry Energy Efficient Computation based on Mixed Dynamic/Transmission-Gate Full Adders 185
Hardware-Efficient PRBGs Based on 1-D Piecewise Linear Chaotic Maps 185
A variability-tolerant feedback technique for throughput maximization of TRBGs with predefined entropy 183
A Simple Keeper Topology to Reduce Delay Variations in Nanometer Domino Logic 179
A general model for differential power analysis attacks to static logic circuits 176
Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits from Experimental Measurements 175
The Digital Tent Map: Performance Analysis and Optimized Design as a Low Complexity Source of Pseudo-Random Bits 175
Trading off static power and dynamic performance in CMOS digital circuits: bulk versus double gate SOI MOSFETs 173
A Novel Back-Biasing Low-Leakage Technique for FinFET Forced Stacks 172
A Simple Strategy for Optimized Design of One-Level Carry-Skip Adders 171
Compact and Simple Output Transition Time Model in Nanometer CMOS Gates 171
Analysis and performance evaluation of area-efficient true random bit generators on FPGAs 171
Uniform-Distributed Noise Generator Based on a Chaotic Circuit 169
Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I-Device-Circuit Interaction and Evaluation at Device Level 169
Power-Delay Optimization of D-Latch/MUX Source Coupled Logic Gates 168
Design in the Energy-Delay Space 168
NAND/NOR Adiabatic Gates: Power Consumption Evaluation and Comparison versus the Fan-In 165
Design of Cascaded ECL Gates with a Power Constraint 165
Optimized Design of Parallel Carry-Select Adders 165
Power-aware design of nanometer MCML tapered buffers 164
Maximum-Period PRNGs Derived From A Piecewise Linear One-Dimensional Map 164
Analysis and design of MCML gates with hysteresis 164
A Simple and Accurate Model of Input capacitance for Power Estimation in CMOS logic 163
A general power model of Differential Power Analysis attacks to static logic circuits 163
Highly Accurate and Simple Models for CML and ECL gates 161
Impact of High-Mobility Materials on the Performance of Near- and Sub-Threshold CMOS Logic Circuits 160
Leakage Power Analysis attacks against a bit slice implementation of the Serpent block cipher2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES) 160
A Class of Maximum-Period Nonlinear Congruential Generators Derived From the Rényi Chaotic Map 157
Techniques to enhance the resistance of precharged busses to differential power analysis 157
"EChO" Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions 157
Positive-Feedback Source-Coupled Logic: a delay model 154
Modeling and Evaluation of Positive-Feedback Source-Coupled Logic 154
A general model of DPA attacks to precharged busses in symmetric-key cryptographic algorithms 153
Understanding the effect of process variations on the delay of static and domino logic 153
Power Estimation in Adiabatic Circuits: A Simple and Accurate Model 153
Optimized design of high fan-in multiplexers using tri-state buffers 152
Exploiting Hysteresys in MCML Circuits 152
Tapered-Vth Approach for Energy-Efficient CMOS Buffers 152
Long Period Pseudo Random Bit Generators Derived from a Discretized Chaotic Map 152
Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison 152
Experimental Study of Leakage-Delay Trade-off in Germanium pMOSFETs for Logic Circuits 151
Analysis of Layout Density in FinFET Standard Cells and Impact of Fin Technology 151
An Efficient Implementation of PRNGs Based on the Digital Sawtooth Map 151
Mixed FBB/RBB: a Novel Low-Leakage Technique for FinFET Forced Stacks 151
Analysis and Modeling of Energy Consumption in RLC Tree Circuits 150
A Design Methodology for High-Speed Low-Power MCML Frequency Dividers 149
Leakage Power Analysis Attacks: Effectiveness on DPA Resistant Logic Styles under Process Variations 149
Closed-Form Analysis of DC Noise Immunity in Subthreshold CMOS Logic Circuits 149
Understanding DC Behavior of Subthreshold CMOS Logic through Closed-Form Analysis 149
Very High-Speed Carry Computation based on Mixed Dynamic/Transmission-Gate Full Adders 149
Performance Evaluation of the Low-Voltage CML D-Latch Topology 148
Design metrics for RTL level estimation of delay variability due to intradie (random) variations 148
Analysis and design of digital PRNGS based on the discretized sawtooth map 148
Analysis and Comparison on Full Adder Block in Sub-Micron Technology 148
Efficient Post-Processing Module for a Chaos-based Random Bit Generator 148
Explicit Energy Evaluation in RLC Tree Circuits with Ramp Inputs 147
Nanometer Flip-Flops Design in the E-D Space 146
Buried Silicon Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits under Aggressive Voltage Scaling 146
Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency Dividers 145
Modeling strategies of the input admittance of RC interconnects for VLSI CAD tools 145
An approach to the design of PFSCL gates 145
CML and ECL: Optimized Design and Comparison 144
Oscillation Frequency in CML and ESCL Ring Oscillators 144
Comparative Evaluation of Layout Density in 3T, 4T and MT FinFET Standard Cells 144
Power Analysis Attacks to Cryptographic Circuits: a Comparative Analysis of DPA and CPA 143
45pW ESD clamp circuit for ultra-low power applicationsProceedings of the IEEE 2013 Custom Integrated Circuits Conference 143
Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects 142
Low-Standby Current 4T FinFET Buffers: Analysis and Evaluation below 45 nm 142
Energy Consumption in RLC Tree Circuits 141
Simple and Accurate Modeling of the Output Transition Time in Nanometer CMOS Gates 141
Leakage Power Analysis Attacks: Well-Defined Procedure and First Experimental Results 141
Mixed Techniques to Protect Precharged Busses against Differential Power Analysis Attacks 140
Optimization of the Wire Grid Size for Differential Routing: Analysis and Impact on the Power-Delay-Area Tradeoff 140
Metrics and Design Considerations on the Energy-Delay Tradeoff of Digital Circuits 139
Delay Estimation of SCL Gates with Output Buffer 138
Analysis of the impact of process variations on static logic circuits versus fan-in 137
Analysis and Design of Ultra-Low Power Subthreshold MCML Gates 137
Performance Evaluation of Adiabatic Gates 137
Clock Distribution in Clock Domains with Dual-Edge-Triggered Flip-Flops to improve Energy-Efficiency 136
Design of Low-Power High-Speed Bipolar Frequency Dividers 136
Analysis and Evaluation of Layout Density of FinFET Logic Gates 135
Improving the Power-Delay Product in SCL Circuits Using Source Follower Output Stage 135
Optimization of Wire Grid Size for Differential Routing and Impact on the Power-Delay-Area Tradeoff 133
Flip-Flop Energy/Performance versus Clock Slope and Impact on the Clock Network Design 133
Power-Aware Design Techniques for Nanometer MOS Current-Mode Logic Gates: a Design Framework 133
Tapered-VTH CMOS Buffer Design for Improved Energy Efficiency in Deep Nanometer Technology 132
Totale 16.232
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Categoria #
all - tutte 72.937
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 72.937
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/20213.710 298 373 212 426 157 380 240 499 474 190 286 175
2021/20221.834 164 296 112 65 90 109 102 55 82 249 159 351
2022/20232.727 179 156 350 426 250 584 55 209 263 131 78 46
2023/20241.305 80 39 93 125 40 360 441 16 7 21 13 70
2024/20253.370 85 198 202 166 370 169 56 239 192 134 379 1.180
2025/2026392 392 0 0 0 0 0 0 0 0 0 0 0
Totale 23.289