IRIS
ALIOTO, MASSIMO BRUNO CRIS
 Distribuzione geografica
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Continente #
NA - Nord America 16.779
EU - Europa 10.349
AS - Asia 5.432
SA - Sud America 1.040
AF - Africa 171
Continente sconosciuto - Info sul continente non disponibili 55
OC - Oceania 10
AN - Antartide 1
Totale 33.837
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Nazione #
US - Stati Uniti d'America 16.542
GB - Regno Unito 2.473
CN - Cina 2.062
DE - Germania 1.891
SG - Singapore 1.483
RU - Federazione Russa 1.338
IE - Irlanda 1.064
UA - Ucraina 950
IT - Italia 939
BR - Brasile 832
FR - Francia 644
SE - Svezia 523
HK - Hong Kong 485
VN - Vietnam 443
KR - Corea 302
FI - Finlandia 226
IN - India 169
ES - Italia 122
CA - Canada 119
TR - Turchia 106
BD - Bangladesh 78
AR - Argentina 69
NG - Nigeria 54
IQ - Iraq 48
MX - Messico 44
ZA - Sudafrica 43
CO - Colombia 39
ID - Indonesia 33
PL - Polonia 32
EC - Ecuador 30
JP - Giappone 29
NL - Olanda 25
PK - Pakistan 24
VE - Venezuela 24
BE - Belgio 23
SA - Arabia Saudita 18
CL - Cile 17
MA - Marocco 17
EG - Egitto 15
JM - Giamaica 15
UZ - Uzbekistan 15
PY - Paraguay 14
CR - Costa Rica 13
EE - Estonia 13
NP - Nepal 13
PH - Filippine 12
AT - Austria 11
RO - Romania 11
AZ - Azerbaigian 10
IR - Iran 10
AE - Emirati Arabi Uniti 9
AU - Australia 9
CZ - Repubblica Ceca 9
EU - Europa 9
HN - Honduras 9
JO - Giordania 9
MY - Malesia 9
TN - Tunisia 9
TT - Trinidad e Tobago 9
BG - Bulgaria 8
PE - Perù 8
TW - Taiwan 8
CH - Svizzera 7
GR - Grecia 7
KE - Kenya 7
LT - Lituania 7
TH - Thailandia 6
BB - Barbados 5
CY - Cipro 5
DZ - Algeria 5
IL - Israele 5
KZ - Kazakistan 5
AM - Armenia 4
BH - Bahrain 4
CI - Costa d'Avorio 4
DO - Repubblica Dominicana 4
GT - Guatemala 4
OM - Oman 4
PT - Portogallo 4
QA - Qatar 4
RS - Serbia 4
UY - Uruguay 4
KG - Kirghizistan 3
MD - Moldavia 3
NI - Nicaragua 3
SY - Repubblica araba siriana 3
AL - Albania 2
AO - Angola 2
BO - Bolivia 2
BS - Bahamas 2
CG - Congo 2
ET - Etiopia 2
GA - Gabon 2
GE - Georgia 2
HU - Ungheria 2
IM - Isola di Man 2
KN - Saint Kitts e Nevis 2
LA - Repubblica Popolare Democratica del Laos 2
LB - Libano 2
LK - Sri Lanka 2
Totale 33.756
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Città #
Southend 2.199
Fairfield 1.932
Ashburn 1.563
Dallas 1.360
Dublin 1.062
Houston 1.061
Woodbridge 926
Jacksonville 779
Seattle 769
Singapore 750
Chandler 735
Wilmington 668
Cambridge 665
Santa Clara 554
Hong Kong 463
Milan 411
Ann Arbor 385
Beijing 384
Council Bluffs 343
San Jose 331
Hefei 326
Princeton 317
Moscow 299
Seoul 295
Nanjing 277
The Dalles 252
Los Angeles 211
Ho Chi Minh City 145
Rome 143
Lauterbourg 141
Hanoi 128
San Diego 122
New York 116
Málaga 107
Boardman 98
Nanchang 92
Buffalo 83
Izmir 80
Shenyang 77
San Mateo 71
Helsinki 59
Columbus 55
São Paulo 53
Hebei 51
Abuja 50
Figino 50
London 50
Siena 50
Chicago 47
Kunming 46
Atlanta 45
Bengaluru 43
Brooklyn 42
Shanghai 42
Tianjin 42
Denver 40
Jiaxing 40
Orem 40
San Francisco 40
Changsha 34
Guangzhou 29
Johannesburg 29
Phoenix 29
Mestre 28
Montreal 28
Toronto 28
Zhengzhou 27
Haiphong 26
Redondo Beach 26
Turin 26
Chennai 25
Frankfurt am Main 25
Warsaw 25
Norwalk 24
Jinan 22
Hangzhou 21
Philadelphia 21
Brasília 20
Dearborn 20
Tokyo 20
Belo Horizonte 19
Boston 19
Newark 19
Brussels 18
Baghdad 17
Bogotá 17
Da Nang 17
Rio de Janeiro 17
Munich 16
Ningbo 16
Stockholm 16
Florence 15
Lanzhou 15
Manchester 15
Miami 15
Vancouver 15
Changchun 14
New Delhi 14
The Bronx 14
Porto Alegre 13
Totale 22.459
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Nome #
"EChO" Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions 1.331
Mixed Full Adder Topologies for High-Performance Low-Power Arithmetic Circuits 484
A Feedback Strategy to Improve the Entropy of a Chaos-Based Random Bit Generator 370
Adiabatic Gates: a Critical Point of View 339
A Class of Maximum-Period Nonlinear Congruential Generators Derived From the Rényi Chaotic Map 326
A scalable low-entropy detector to counteract the parameter variability effects in TRBGs 294
Evaluation of Energy Consumption in RC Ladder Circuits Driven by a Ramp Input 293
A technique to design high entropy chaos-based true random bit generators 283
A general power model of Differential Power Analysis attacks to static logic circuits 283
13.8 A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 282
Implementation Efficient Maximum-Period Nonlinear Congruential Generators 281
Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial 280
A general model for differential power analysis attacks to static logic circuits 278
A general model of DPA attacks to precharged busses in symmetric-key cryptographic algorithms 277
A Simple Keeper Topology to Reduce Delay Variations in Nanometer Domino Logic 273
Modeling and Optimized Design of Current Mode MUX/XOR and D Flip-Flop 268
A variability-tolerant feedback technique for throughput maximization of TRBGs with predefined entropy 267
A Novel Back-Biasing Low-Leakage Technique for FinFET Forced Stacks 267
Exploiting Locality to Improve Leakage Reduction in Embedded Drowsy I-Caches at Same Area/Speed 267
Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under Process Variations 264
A Simple Strategy for Optimized Design of One-Level Carry-Skip Adders 260
Design Strategies for Source Coupled Logic Gates 252
A Simple and Accurate Model of Input capacitance for Power Estimation in CMOS logic 252
Power-Delay Optimization of D-Latch/MUX Source Coupled Logic Gates 248
A Design Methodology for High-Speed Low-Power MCML Frequency Dividers 247
An approach to the design of PFSCL gates 240
Analysis and design of MCML gates with hysteresis 240
An Efficient Implementation of PRNGs Based on the Digital Sawtooth Map 238
The Digital Tent Map: Performance Analysis and Optimized Design as a Source of Pseudo-Random Bits 238
Hardware-Efficient PRBGs Based on 1-D Piecewise Linear Chaotic Maps 237
The Digital Tent Map: Performance Analysis and Optimized Design as a Low Complexity Source of Pseudo-Random Bits 231
NAND/NOR Adiabatic Gates: Power Consumption Evaluation and Comparison versus the Fan-In 230
Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study 230
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies 229
Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits from Experimental Measurements 226
Compact and Simple Output Transition Time Model in Nanometer CMOS Gates 225
45pW ESD clamp circuit for ultra-low power applicationsProceedings of the IEEE 2013 Custom Integrated Circuits Conference 225
Exploiting Hysteresys in MCML Circuits 223
Very Fast Carry Energy Efficient Computation based on Mixed Dynamic/Transmission-Gate Full Adders 221
Power Estimation in Adiabatic Circuits: A Simple and Accurate Model 221
Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I-Device-Circuit Interaction and Evaluation at Device Level 217
Trading off static power and dynamic performance in CMOS digital circuits: bulk versus double gate SOI MOSFETs 217
Power-aware design of nanometer MCML tapered buffers 215
Uniform-Distributed Noise Generator Based on a Chaotic Circuit 215
Maximum-Period PRNGs Derived From A Piecewise Linear One-Dimensional Map 214
Understanding the effect of process variations on the delay of static and domino logic 214
Power-Aware Design Techniques for Nanometer MOS Current-Mode Logic Gates: a Design Framework 212
Mixed Techniques to Protect Precharged Busses against Differential Power Analysis Attacks 211
Design of Cascaded ECL Gates with a Power Constraint 210
Analysis and Comparison on Full Adder Block in Sub-Micron Technology 210
Design in the Energy-Delay Space 209
Analysis and performance evaluation of area-efficient true random bit generators on FPGAs 209
Highly Accurate and Simple Models for CML and ECL gates 208
Impact of High-Mobility Materials on the Performance of Near- and Sub-Threshold CMOS Logic Circuits 207
Performance Evaluation of the Low-Voltage CML D-Latch Topology 206
Power Analysis Attacks to Cryptographic Circuits: a Comparative Analysis of DPA and CPA 206
Metrics and Design Considerations on the Energy-Delay Tradeoff of Digital Circuits 205
Techniques to enhance the resistance of precharged busses to differential power analysis 205
Analysis of Layout Density in FinFET Standard Cells and Impact of Fin Technology 205
Positive-Feedback Source-Coupled Logic: a delay model 205
Understanding DC Behavior of Subthreshold CMOS Logic through Closed-Form Analysis 202
Nanometer Flip-Flops Design in the E-D Space 201
Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison 201
Explicit Energy Evaluation in RLC Tree Circuits with Ramp Inputs 201
Optimized Design of Parallel Carry-Select Adders 200
Tapered-Vth Approach for Energy-Efficient CMOS Buffers 200
Analysis and design of digital PRNGS based on the discretized sawtooth map 200
Closed-Form Analysis of DC Noise Immunity in Subthreshold CMOS Logic Circuits 200
Mixed FBB/RBB: a Novel Low-Leakage Technique for FinFET Forced Stacks 200
Comparative Evaluation of Layout Density in 3T, 4T and MT FinFET Standard Cells 199
Experimental Study of Leakage-Delay Trade-off in Germanium pMOSFETs for Logic Circuits 199
Analysis and Design of Ultra-Low Power Subthreshold MCML Gates 199
Oscillation Frequency in CML and ESCL Ring Oscillators 198
Analysis and Modeling of Energy Consumption in RLC Tree Circuits 198
Leakage Power Analysis Attacks: Effectiveness on DPA Resistant Logic Styles under Process Variations 197
Efficient Post-Processing Module for a Chaos-based Random Bit Generator 197
Delay Estimation of SCL Gates with Output Buffer 196
Optimized design of high fan-in multiplexers using tri-state buffers 195
Analysis and Evaluation of Layout Density of FinFET Logic Gates 195
Leakage Power Analysis Attacks: Well-Defined Procedure and First Experimental Results 194
Energy Consumption in RLC Tree Circuits 193
Modeling strategies of the input admittance of RC interconnects for VLSI CAD tools 193
Long Period Pseudo Random Bit Generators Derived from a Discretized Chaotic Map 193
Flip-Flop Energy/Performance versus Clock Slope and Impact on the Clock Network Design 192
Buried Silicon Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits under Aggressive Voltage Scaling 192
Simple and Accurate Modeling of the Output Transition Time in Nanometer CMOS Gates 192
Leakage Power Analysis attacks against a bit slice implementation of the Serpent block cipher2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES) 192
Analysis of the impact of process variations on static logic circuits versus fan-in 191
Impact of Clock Slope on Energy/Delay of Pulsed Flip-Flops and Optimum Clock Domain Design 191
Design metrics for RTL level estimation of delay variability due to intradie (random) variations 191
Modeling and Evaluation of Positive-Feedback Source-Coupled Logic 191
Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency Dividers 190
Very High-Speed Carry Computation based on Mixed Dynamic/Transmission-Gate Full Adders 190
Performance Evaluation of Adiabatic Gates 189
Design of Low-Power High-Speed Bipolar Frequency Dividers 189
Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects 187
Power–Delay–Area–Noise Margin Tradeoffs in Positive-Feedback MOS Current-Mode Logic 183
Improving the Power-Delay Product in SCL Circuits Using Source Follower Output Stage 183
Low-Standby Current 4T FinFET Buffers: Analysis and Evaluation below 45 nm 183
CML and ECL: Optimized Design and Comparison 182
Totale 23.679
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Categoria #
all - tutte 98.964
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 98.964
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2021/20221.262 0 0 0 65 90 109 102 55 82 249 159 351
2022/20232.727 179 156 350 426 250 584 55 209 263 131 78 46
2023/20241.305 80 39 93 125 40 360 441 16 7 21 13 70
2024/20253.370 85 198 202 166 370 169 56 239 192 134 379 1.180
2025/20268.869 666 1.338 914 684 1.123 277 877 223 243 526 1.176 822
2026/20272.071 488 483 995 105 0 0 0 0 0 0 0 0
Totale 33.837