IRIS
ALIOTO, MASSIMO BRUNO CRIS
 Distribuzione geografica
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Continente #
NA - Nord America 13.221
EU - Europa 9.242
AS - Asia 4.269
SA - Sud America 838
AF - Africa 83
Continente sconosciuto - Info sul continente non disponibili 9
OC - Oceania 9
AN - Antartide 1
Totale 27.672
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Nazione #
US - Stati Uniti d'America 13.130
GB - Regno Unito 2.395
CN - Cina 1.881
DE - Germania 1.856
RU - Federazione Russa 1.336
SG - Singapore 1.096
IE - Irlanda 1.061
UA - Ucraina 948
BR - Brasile 729
SE - Svezia 521
FR - Francia 483
HK - Hong Kong 411
KR - Corea 297
FI - Finlandia 221
IT - Italia 166
VN - Vietnam 163
ES - Italia 118
IN - India 114
TR - Turchia 96
AR - Argentina 57
CA - Canada 47
BD - Bangladesh 33
IQ - Iraq 32
ZA - Sudafrica 31
PL - Polonia 25
MX - Messico 23
BE - Belgio 21
NL - Olanda 21
JP - Giappone 20
ID - Indonesia 19
PK - Pakistan 14
MA - Marocco 12
PY - Paraguay 11
EC - Ecuador 10
VE - Venezuela 10
EG - Egitto 9
EU - Europa 9
IR - Iran 9
RO - Romania 9
SA - Arabia Saudita 9
UZ - Uzbekistan 9
AU - Australia 8
CO - Colombia 8
TW - Taiwan 8
AZ - Azerbaigian 7
BG - Bulgaria 7
CH - Svizzera 7
CZ - Repubblica Ceca 7
EE - Estonia 6
GR - Grecia 6
KE - Kenya 5
LT - Lituania 5
NP - Nepal 5
TN - Tunisia 5
AE - Emirati Arabi Uniti 4
AM - Armenia 4
AT - Austria 4
CL - Cile 4
CY - Cipro 4
DZ - Algeria 4
IL - Israele 4
JO - Giordania 4
NG - Nigeria 4
PE - Perù 4
TH - Thailandia 4
BB - Barbados 3
BH - Bahrain 3
CI - Costa d'Avorio 3
HN - Honduras 3
PH - Filippine 3
PT - Portogallo 3
RS - Serbia 3
UY - Uruguay 3
AO - Angola 2
CR - Costa Rica 2
DO - Repubblica Dominicana 2
GT - Guatemala 2
HU - Ungheria 2
IM - Isola di Man 2
JM - Giamaica 2
KG - Kirghizistan 2
KN - Saint Kitts e Nevis 2
KZ - Kazakistan 2
LA - Repubblica Popolare Democratica del Laos 2
MD - Moldavia 2
MY - Malesia 2
NI - Nicaragua 2
OM - Oman 2
TT - Trinidad e Tobago 2
TZ - Tanzania 2
AL - Albania 1
AQ - Antartide 1
BN - Brunei Darussalam 1
BO - Bolivia 1
BS - Bahamas 1
BW - Botswana 1
DK - Danimarca 1
ET - Etiopia 1
GE - Georgia 1
GM - Gambi 1
Totale 27.658
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Città #
Southend 2.199
Fairfield 1.930
Dallas 1.252
Dublin 1.059
Houston 1.037
Ashburn 996
Woodbridge 924
Jacksonville 771
Seattle 760
Chandler 735
Wilmington 667
Cambridge 665
Singapore 592
Santa Clara 445
Hong Kong 405
Ann Arbor 385
Beijing 363
Princeton 316
Moscow 299
Seoul 295
Nanjing 277
Hefei 258
San Diego 119
Los Angeles 109
Málaga 107
Boardman 98
Nanchang 92
The Dalles 91
Buffalo 79
Izmir 79
Shenyang 77
Council Bluffs 72
San Mateo 71
Ho Chi Minh City 64
Helsinki 54
Hebei 51
Siena 50
São Paulo 50
Kunming 46
Bengaluru 43
New York 43
Tianjin 42
Jiaxing 40
Shanghai 39
London 37
Hanoi 34
Changsha 33
Columbus 30
Guangzhou 29
Mestre 28
Redondo Beach 26
Zhengzhou 26
Chicago 23
Norwalk 23
Jinan 22
Hangzhou 20
Belo Horizonte 19
Dearborn 19
Johannesburg 19
Toronto 19
Warsaw 19
Brussels 18
Brooklyn 17
Rio de Janeiro 17
San Francisco 17
Ningbo 16
Stockholm 16
Munich 15
Baghdad 14
Lanzhou 14
Changchun 13
Chennai 13
Porto Alegre 12
Redwood City 12
Tokyo 12
Curitiba 11
Tappahannock 11
Brasília 10
Manchester 10
New Delhi 10
Philadelphia 10
Shenzhen 10
Boston 9
Campinas 9
Haiphong 9
Jundiaí 9
Atlanta 8
Charlotte 8
Denver 8
Florence 8
Montreal 8
Ribeirão Preto 8
Rome 8
Baku 7
Dhaka 7
Frankfurt am Main 7
Grünheide 7
Guarulhos 7
Santo André 7
Taizhou 7
Totale 18.991
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Nome #
Mixed Full Adder Topologies for High-Performance Low-Power Arithmetic Circuits 443
A Feedback Strategy to Improve the Entropy of a Chaos-Based Random Bit Generator 317
A Class of Maximum-Period Nonlinear Congruential Generators Derived From the Rényi Chaotic Map 283
A technique to design high entropy chaos-based true random bit generators 257
A scalable low-entropy detector to counteract the parameter variability effects in TRBGs 257
Implementation Efficient Maximum-Period Nonlinear Congruential Generators 256
Evaluation of Energy Consumption in RC Ladder Circuits Driven by a Ramp Input 250
A general power model of Differential Power Analysis attacks to static logic circuits 243
13.8 A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 243
Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial 242
A general model for differential power analysis attacks to static logic circuits 241
Exploiting Locality to Improve Leakage Reduction in Embedded Drowsy I-Caches at Same Area/Speed 240
A variability-tolerant feedback technique for throughput maximization of TRBGs with predefined entropy 235
A general model of DPA attacks to precharged busses in symmetric-key cryptographic algorithms 233
A Novel Back-Biasing Low-Leakage Technique for FinFET Forced Stacks 230
A Simple Keeper Topology to Reduce Delay Variations in Nanometer Domino Logic 230
Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under Process Variations 229
A Simple Strategy for Optimized Design of One-Level Carry-Skip Adders 220
Modeling and Optimized Design of Current Mode MUX/XOR and D Flip-Flop 220
"EChO" Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions 220
A Simple and Accurate Model of Input capacitance for Power Estimation in CMOS logic 218
Design Strategies for Source Coupled Logic Gates 214
Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study 212
The Digital Tent Map: Performance Analysis and Optimized Design as a Source of Pseudo-Random Bits 209
Hardware-Efficient PRBGs Based on 1-D Piecewise Linear Chaotic Maps 208
The Digital Tent Map: Performance Analysis and Optimized Design as a Low Complexity Source of Pseudo-Random Bits 207
Compact and Simple Output Transition Time Model in Nanometer CMOS Gates 205
Very Fast Carry Energy Efficient Computation based on Mixed Dynamic/Transmission-Gate Full Adders 204
An approach to the design of PFSCL gates 203
Analysis and design of MCML gates with hysteresis 203
NAND/NOR Adiabatic Gates: Power Consumption Evaluation and Comparison versus the Fan-In 199
A Design Methodology for High-Speed Low-Power MCML Frequency Dividers 199
Power-Delay Optimization of D-Latch/MUX Source Coupled Logic Gates 198
Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits from Experimental Measurements 198
An Efficient Implementation of PRNGs Based on the Digital Sawtooth Map 197
45pW ESD clamp circuit for ultra-low power applicationsProceedings of the IEEE 2013 Custom Integrated Circuits Conference 196
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies 195
Uniform-Distributed Noise Generator Based on a Chaotic Circuit 192
Trading off static power and dynamic performance in CMOS digital circuits: bulk versus double gate SOI MOSFETs 189
Design in the Energy-Delay Space 186
Design of Cascaded ECL Gates with a Power Constraint 185
Maximum-Period PRNGs Derived From A Piecewise Linear One-Dimensional Map 185
Power-aware design of nanometer MCML tapered buffers 184
Optimized Design of Parallel Carry-Select Adders 182
Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I-Device-Circuit Interaction and Evaluation at Device Level 182
Analysis and performance evaluation of area-efficient true random bit generators on FPGAs 182
Power Estimation in Adiabatic Circuits: A Simple and Accurate Model 182
Positive-Feedback Source-Coupled Logic: a delay model 181
Highly Accurate and Simple Models for CML and ECL gates 180
Analysis of Layout Density in FinFET Standard Cells and Impact of Fin Technology 179
Performance Evaluation of the Low-Voltage CML D-Latch Topology 177
Techniques to enhance the resistance of precharged busses to differential power analysis 177
Analysis and design of digital PRNGS based on the discretized sawtooth map 177
Impact of High-Mobility Materials on the Performance of Near- and Sub-Threshold CMOS Logic Circuits 177
Tapered-Vth Approach for Energy-Efficient CMOS Buffers 174
Analysis and Modeling of Energy Consumption in RLC Tree Circuits 174
Optimized design of high fan-in multiplexers using tri-state buffers 173
Exploiting Hysteresys in MCML Circuits 173
Modeling strategies of the input admittance of RC interconnects for VLSI CAD tools 173
Mixed Techniques to Protect Precharged Busses against Differential Power Analysis Attacks 173
Power Analysis Attacks to Cryptographic Circuits: a Comparative Analysis of DPA and CPA 172
Leakage Power Analysis attacks against a bit slice implementation of the Serpent block cipher2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES) 172
Oscillation Frequency in CML and ESCL Ring Oscillators 171
Long Period Pseudo Random Bit Generators Derived from a Discretized Chaotic Map 171
Understanding the effect of process variations on the delay of static and domino logic 171
Explicit Energy Evaluation in RLC Tree Circuits with Ramp Inputs 171
Modeling and Evaluation of Positive-Feedback Source-Coupled Logic 170
Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency Dividers 169
Energy Consumption in RLC Tree Circuits 169
Buried Silicon Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits under Aggressive Voltage Scaling 169
Experimental Study of Leakage-Delay Trade-off in Germanium pMOSFETs for Logic Circuits 168
Design metrics for RTL level estimation of delay variability due to intradie (random) variations 168
Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects 168
Analysis and Comparison on Full Adder Block in Sub-Micron Technology 168
Understanding DC Behavior of Subthreshold CMOS Logic through Closed-Form Analysis 168
Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison 168
Comparative Evaluation of Layout Density in 3T, 4T and MT FinFET Standard Cells 167
Analysis of the impact of process variations on static logic circuits versus fan-in 167
Delay Estimation of SCL Gates with Output Buffer 167
Nanometer Flip-Flops Design in the E-D Space 167
Leakage Power Analysis Attacks: Effectiveness on DPA Resistant Logic Styles under Process Variations 167
CML and ECL: Optimized Design and Comparison 165
Analysis and Evaluation of Layout Density of FinFET Logic Gates 165
Closed-Form Analysis of DC Noise Immunity in Subthreshold CMOS Logic Circuits 165
Mixed FBB/RBB: a Novel Low-Leakage Technique for FinFET Forced Stacks 165
Metrics and Design Considerations on the Energy-Delay Tradeoff of Digital Circuits 164
Efficient Post-Processing Module for a Chaos-based Random Bit Generator 164
Simple and Accurate Modeling of the Output Transition Time in Nanometer CMOS Gates 163
Flip-Flop Energy/Performance versus Clock Slope and Impact on the Clock Network Design 159
Leakage Power Analysis Attacks: Well-Defined Procedure and First Experimental Results 159
Adiabatic Gates: a Critical Point of View 158
Very High-Speed Carry Computation based on Mixed Dynamic/Transmission-Gate Full Adders 158
Power-Aware Design Techniques for Nanometer MOS Current-Mode Logic Gates: a Design Framework 157
Improving the Power-Delay Product in SCL Circuits Using Source Follower Output Stage 156
Design of MUX, XOR and D-Latch SCL gates 155
Analysis and Design of Ultra-Low Power Subthreshold MCML Gates 155
Optimization of the Wire Grid Size for Differential Routing: Analysis and Impact on the Power-Delay-Area Tradeoff 155
Low-Standby Current 4T FinFET Buffers: Analysis and Evaluation below 45 nm 154
Design of Low-Power High-Speed Bipolar Frequency Dividers 154
High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology 153
Totale 19.263
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Categoria #
all - tutte 82.974
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 82.974
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/20212.244 0 0 0 0 0 380 240 499 474 190 286 175
2021/20221.834 164 296 112 65 90 109 102 55 82 249 159 351
2022/20232.727 179 156 350 426 250 584 55 209 263 131 78 46
2023/20241.305 80 39 93 125 40 360 441 16 7 21 13 70
2024/20253.370 85 198 202 166 370 169 56 239 192 134 379 1.180
2025/20264.821 666 1.338 914 684 1.123 96 0 0 0 0 0 0
Totale 27.718