Design strategies for PFSCL (positive feedback source-coupled logic) gates are discussed. Criteria to size transistor aspect ratios and bias currents are derived as a function of the requirements on the noise margin and the power-delay trade-off, which are analytically modeled. The design criteria are also discussed in cases which are of practical interest, i.e., when a high speed or an optimum balance with power dissipation is required. The proposed design strategies are simple enough to be used in pencil-and-paper calculations. The theoretical results are validated through simulations on a 0.18-μm CMOS process.
Alioto, M.B.C., Fort, A., Pancioni, L., Rocchi, S., Vignoli, V. (2005). An approach to the design of PFSCL gates. In Proceedings of the 2005 IEEE International Symposium on Circuits and Systems (ISCAS 2005) (pp.2437-2440). New York, USA : IEEE [10.1109/ISCAS.2005.1465118].
An approach to the design of PFSCL gates
ALIOTO, MASSIMO BRUNO CRIS;FORT, ADA;PANCIONI, LUCA;ROCCHI, SANTINA;VIGNOLI, VALERIO
2005-01-01
Abstract
Design strategies for PFSCL (positive feedback source-coupled logic) gates are discussed. Criteria to size transistor aspect ratios and bias currents are derived as a function of the requirements on the noise margin and the power-delay trade-off, which are analytically modeled. The design criteria are also discussed in cases which are of practical interest, i.e., when a high speed or an optimum balance with power dissipation is required. The proposed design strategies are simple enough to be used in pencil-and-paper calculations. The theoretical results are validated through simulations on a 0.18-μm CMOS process.File | Dimensione | Formato | |
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https://hdl.handle.net/11365/34396
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