In this paper a strategy to design paths consisting of cascaded bipolar CML gates is proposed. In particular, explicit design criteria are derived both for low-power non-critical paths and high-speed critical paths. The analytical results are simple to be applied to actual circuits avoiding the usual time-consuming approach based on iterative simulations with a trial-and-error procedure. Moreover, it provides the designer with a deeper understanding of the power-delay trade-off. Design examples based on a 20-GHz bipolar process are introduced to validate the procedure and clarify its application.
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|Titolo:||Design strategies of Cascaded CML Gates|
|Rivista:||IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS|
|Citazione:||Alioto, M.B.C., & Palumbo, G. (2006). Design strategies of Cascaded CML Gates. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS, 53(2), 85-89.|
|Appare nelle tipologie:||1.1 Articolo in rivista|