Power-Delay Optimization of D-Latch/MUX Source Coupled Logic Gates

In this paper a design strategy for MUX, XOR and D-latch Source-Coupled Logic (SCL) gates is proposed. To this end, an analytical model of the delay and the noise margin as a function of the transistors’ aspect ratio and bias current is first introduced. Successively, analytical equations of the transistors’ aspect ratio to meet a given noise margin specification are derived as a function of the bias current, and are then used along with the delay model to express the delay as an explicit function of the bias current and noise margin. The simplified delay expression explicitly relates speed performance to power dissipation and the noise margin, thereby providing the designer with the required understanding of the trade-offs involved in the design. Therefore, the criteria proposed allow the designer to consciously manage the power-delay trade-off. The delay dependence on the logic swing is also investigated with results showing that this delay is not necessarily reduced by reducing the logic swing, in contrast with the usual assumption. Since the results obtained are valid for all SCL gates and are independent of the CMOS process used, the guidelines provided afford a deeper understanding of SCL gates from a design point of view.