In the paper the buffer and the NAND/NOR adiabatic gate are compared with that designed with the traditional CMOS approach. The comparison is made both assuming an assigned power supply and setting its value to minimize the power consumption. General relationship independent from process parameter, which are also simple to be useful in a pencil-and-paper evaluation, are carried out. Analytical results are validate with Spice Simulations by using 0.8-m CMOS technology. The analysis show that with the considered technology and a fan-out of three, the adiabatic buffer is advantageous for frequency lower than 167 MHz and 21 MHz for the non optimized and the optimized design, respectively. These frequencies lower to 23 MHz and 1.3 MHz for the NAND/NOR gate. Moreover all the frequency reduce linearly increasing the fan out of the gate.

Alioto, M.B.C., Palumbo, G. (2000). Performance Evaluation of Adiabatic Gates. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I. FUNDAMENTAL THEORY AND APPLICATIONS, 47(9), 1297-1308.

Performance Evaluation of Adiabatic Gates

ALIOTO, MASSIMO BRUNO CRIS;
2000-01-01

Abstract

In the paper the buffer and the NAND/NOR adiabatic gate are compared with that designed with the traditional CMOS approach. The comparison is made both assuming an assigned power supply and setting its value to minimize the power consumption. General relationship independent from process parameter, which are also simple to be useful in a pencil-and-paper evaluation, are carried out. Analytical results are validate with Spice Simulations by using 0.8-m CMOS technology. The analysis show that with the considered technology and a fan-out of three, the adiabatic buffer is advantageous for frequency lower than 167 MHz and 21 MHz for the non optimized and the optimized design, respectively. These frequencies lower to 23 MHz and 1.3 MHz for the NAND/NOR gate. Moreover all the frequency reduce linearly increasing the fan out of the gate.
2000
Alioto, M.B.C., Palumbo, G. (2000). Performance Evaluation of Adiabatic Gates. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I. FUNDAMENTAL THEORY AND APPLICATIONS, 47(9), 1297-1308.
File in questo prodotto:
File Dimensione Formato  
J4-Performance evaluation of adiabatic gates.pdf

non disponibili

Tipologia: Post-print
Licenza: NON PUBBLICO - Accesso privato/ristretto
Dimensione 427 kB
Formato Adobe PDF
427 kB Adobe PDF   Visualizza/Apri   Richiedi una copia

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11365/36715
 Attenzione

Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo