In this paper, the effect of process variations on the delay of CMOS static logic circuits is discussed versus fan-in. In particular, the effect of process variations in stacked transistors (which determine the fan-in) is analytically evaluated. From circuit analysis, a simple analytical model is derived that expresses the delay variation as a function of the number of stacked transistors and transistor size. Theoretical results are useful to gain an insight into the dependence of the delay variation on design parameters. Monte Carlo simulations on a 90-nm technology were performed to validate the results. © 2008 IEEE.
Alioto, M., Palumbo, G., Pennisi, M. (2008). Analysis of the impact of process variations on static logic circuits versus fan-in. In Proc. of ICECS 2008 (pp.137-140). IEEE [10.1109/ICECS.2008.4674810].
Analysis of the impact of process variations on static logic circuits versus fan-in
Alioto, Massimo;
2008-01-01
Abstract
In this paper, the effect of process variations on the delay of CMOS static logic circuits is discussed versus fan-in. In particular, the effect of process variations in stacked transistors (which determine the fan-in) is analytically evaluated. From circuit analysis, a simple analytical model is derived that expresses the delay variation as a function of the number of stacked transistors and transistor size. Theoretical results are useful to gain an insight into the dependence of the delay variation on design parameters. Monte Carlo simulations on a 90-nm technology were performed to validate the results. © 2008 IEEE.
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https://hdl.handle.net/11365/17299
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