In this paper, subthreshold static CMOS logic is analyzed in terms of DC noise immunity in a closed form for the first time. Simplified circuit models of MOS transistors in subthreshold are developed to gain a deeper understanding of the degradation in the DC characteristics under ultra-low voltages, as well as its dependence on design and process parameters. The noise margin is explicitly evaluated and modeled with a simple expression. The impact of PMOS/NMOS imbalance is also explicitly analyzed. Results are validated with simulations in a 65-nm CMOS technology.
Alioto, M. (2010). Closed-Form Analysis of DC Noise Immunity in Subthreshold CMOS Logic Circuits. In Proc. of ISCAS 2010 (pp.1468-1471). IEEE [10.1109/ISCAS.2010.5537340].
Closed-Form Analysis of DC Noise Immunity in Subthreshold CMOS Logic Circuits
Alioto M.
2010-01-01
Abstract
In this paper, subthreshold static CMOS logic is analyzed in terms of DC noise immunity in a closed form for the first time. Simplified circuit models of MOS transistors in subthreshold are developed to gain a deeper understanding of the degradation in the DC characteristics under ultra-low voltages, as well as its dependence on design and process parameters. The noise margin is explicitly evaluated and modeled with a simple expression. The impact of PMOS/NMOS imbalance is also explicitly analyzed. Results are validated with simulations in a 65-nm CMOS technology.
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https://hdl.handle.net/11365/35613
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