Mixed Full Adder Topologies for High-Performance Low-Power Arithmetic Circuits

This paper deals with the implementation of Full Adder chains by mixing different CMOS Full Adder topologies. The approach is based on cascading fast Transmission-Gate Full Adders interrupted by static gates having driving capability, such as inverters or Mirror Full Adders, thus exploiting the intrinsic low power consumption of such topologies. The obtained mixed-topology circuits are optimized in terms of delay by resorting to simple analytical models. Delay, power consumption and the power-delay product in both mixed-topology and traditional Full Adder chains were evaluated through post-layout Spectre simulations with a 0.35-m, 0.18-m and 90-nm CMOS technology considering different design targets, i.e. minimum power consumption, power-delay product, energy-delay product and delay. The results obtained show that the mixed-topology approach based on Mirror adders are capable of a very low power consumption (comparable to that of the low-power Transmission-Gate Full Adder) and a very high speed (comparable with or even greater than that of the very fast Dual-Rail Domino Full Adder). This also enables a high degree of design freedom, given that the same (mixed) topology can be used for a wide range of applications. This greater flexibility also affords a significant reduction in the design effort.