In this paper, an optimization strategy is proposed for Dual Edge-Triggered (DET) clock distribution in clock domains, based on the proper choice of the clock slope. The suggested approach takes full advantage of the intrinsic features of DET Flip-Flops to achieve up to 50% energy-savings compared to traditional DET design approaches. The speed penalty, in terms of both FFs delay and local skew/jitter, is proven to be negligible through extensive simulations in a 65-nm CMOS technology.
Alioto, M.B.C., E., C., G., P. (2010). Clock Distribution in Clock Domains with Dual-Edge-Triggered Flip-Flops to improve Energy-Efficiency. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (pp.321-324). New York : IEEE [10.1109/ISCAS.2010.5537828].
Clock Distribution in Clock Domains with Dual-Edge-Triggered Flip-Flops to improve Energy-Efficiency
ALIOTO, MASSIMO BRUNO CRIS;
2010-01-01
Abstract
In this paper, an optimization strategy is proposed for Dual Edge-Triggered (DET) clock distribution in clock domains, based on the proper choice of the clock slope. The suggested approach takes full advantage of the intrinsic features of DET Flip-Flops to achieve up to 50% energy-savings compared to traditional DET design approaches. The speed penalty, in terms of both FFs delay and local skew/jitter, is proven to be negligible through extensive simulations in a 65-nm CMOS technology.
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https://hdl.handle.net/11365/35948
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