Optimized Design of Parallel Carry-Select Adders

In this paper a novel gate-level strategy for designing Carry Select adders is proposed. The strategy is more general than the previously proposed techniques, and accounts for the dependence of multiplexer delay on its fan-out. Moreover, the strategy is simple and systematic, and is helpful for designing Carry Select adders with a pencil-and-paper approach. An approximate expression of the minimum delay achievable is derived to estimate performance before carrying out the design. The proposed strategy is validated in more than 1,000 adders. Analysis confirms that the strategy leads to a delay which is minimal in most cases, and always within 5.7%.