This article explores the effect of using source follower buffers (SFB) at the output of source coupled logic (SCL) circuits. This technique can help to improve the power-delay product (PDP) of an SCL gate approximately by a factor of two. The proposed approach has been applied to improve the PDP in sub-threshold SCL circuits that have been developed for ultra-low power applications. Designed in conventional digital 0.18μm CMOS technology, the proposed SCL gate utilizing SFB at the output achieves a PDP of 0.5fJ/fF/gate while the gate draws 10nA from a 0.6V supply voltage. ©2008 IEEE.
Tajalli, A., Gurkaynak, F.K., Leblebici, Y., Alioto, M., Brauer, E.J. (2008). Improving the Power-Delay Product in SCL Circuits Using Source Follower Output Stage. In Proc. of ISCAS 2008 (pp.145-148). IEEE [10.1109/ISCAS.2008.4541375].
Improving the Power-Delay Product in SCL Circuits Using Source Follower Output Stage
Alioto, Massimo;
2008-01-01
Abstract
This article explores the effect of using source follower buffers (SFB) at the output of source coupled logic (SCL) circuits. This technique can help to improve the power-delay product (PDP) of an SCL gate approximately by a factor of two. The proposed approach has been applied to improve the PDP in sub-threshold SCL circuits that have been developed for ultra-low power applications. Designed in conventional digital 0.18μm CMOS technology, the proposed SCL gate utilizing SFB at the output achieves a PDP of 0.5fJ/fF/gate while the gate draws 10nA from a 0.6V supply voltage. ©2008 IEEE.
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https://hdl.handle.net/11365/17296
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