Delay Estimation of SCL Gates with Output Buffer

In this communication a strategy to analytically model propagation delay in CMOS SCL gates with output buffer is proposed. The model is obtained by a suitable linearization of the circuit and assuming a dominant-pole behavior. The delay expressions obtained are related to design and process parameters in a simple way. Since they also have an evident physical meaning, the model allows deep understanding of the SCL circuits behavior and hence they are helpful since the earliest design phases. The accuracy of the model has been checked by simulating an SCL inverter under various bias and load conditions. The error obtained in realistic cases is lower than 20%.