This paper presents a model of the output transition time suitable for nanometer CMOS gates. The proposed modeling approach separately analyzes the output transition time under fast and slow inputs, according to the basic concept of the model in. The model so developed is very simple and preserves a clear physical meaning. These highly desirable characteristics allow for an efficient implementation in CAD tools, as well as an easy scalability between different processes. Spectre simulations on a 45 nm Berkeley Predictive Technology Model (BPTM) show that the model accuracy is about 4%.
Alioto, M.B.C., M., P., G., P. (2008). Compact and Simple Output Transition Time Model in Nanometer CMOS Gates. In Proc. of ICM 2008 (pp.264-267). New York : IEEE [10.1109/ICM.2008.5393823].
Compact and Simple Output Transition Time Model in Nanometer CMOS Gates
ALIOTO, MASSIMO BRUNO CRIS;
2008-01-01
Abstract
This paper presents a model of the output transition time suitable for nanometer CMOS gates. The proposed modeling approach separately analyzes the output transition time under fast and slow inputs, according to the basic concept of the model in. The model so developed is very simple and preserves a clear physical meaning. These highly desirable characteristics allow for an efficient implementation in CAD tools, as well as an easy scalability between different processes. Spectre simulations on a 45 nm Berkeley Predictive Technology Model (BPTM) show that the model accuracy is about 4%.
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https://hdl.handle.net/11365/17395
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