In the paper the buffer and the NAND/NOR adiabatic gate are compared with that designed with the traditional CMOS approach. The comparison is made both assuming an assigned power supply and setting its value to minimize the power consumption. General relationship independent from process parameter, which are also simple to be useful in a pencil-and-paper evaluation, are carried out. Analytical results are validate with Spice Simulations by using 0.8-m CMOS technology. The analysis show that with the considered technology and a fan-out of three, the adiabatic buffer is advantageous for frequency lower than 167 MHz and 21 MHz for the non optimized and the optimized design, respectively. These frequencies lower to 23 MHz and 1.3 MHz for the NAND/NOR gate. Moreover all the frequency reduce linearly increasing the fan out of the gate.
Scheda prodotto non validato
Scheda prodotto in fase di analisi da parte dello staff di validazione
|Titolo:||NAND/NOR Adiabatic Gates: Power Consumption Evaluation and Comparison versus the Fan-In|
|Rivista:||IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I. FUNDAMENTAL THEORY AND APPLICATIONS|
|Citazione:||Alioto, M.B.C., & Palumbo, G. (2002). NAND/NOR Adiabatic Gates: Power Consumption Evaluation and Comparison versus the Fan-In. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I. FUNDAMENTAL THEORY AND APPLICATIONS, 49(9), 1253-1262.|
|Appare nelle tipologie:||1.1 Articolo in rivista|