A design strategy to optimize the bias currents of low-power cascaded ECL gates is discussed. The results can be applied when a power constraint is assigned, and the available current per gate is much lower than the value which minimizes the propagation delay. The strategy is independent of the process used and is suitable for hand calculations, avoiding the trial-and-error approach based on simulations. Design examples based on a 20 GHz bipolar process are also given.

Alioto, M.B.C., GRASSO A., D., & Palumbo, G. (2006). Design of Cascaded ECL Gates with a Power Constraint. ELECTRONICS LETTERS, 42(4), 211-213 [10.1049/el:20064002].

Design of Cascaded ECL Gates with a Power Constraint

ALIOTO, MASSIMO BRUNO CRIS;
2006

Abstract

A design strategy to optimize the bias currents of low-power cascaded ECL gates is discussed. The results can be applied when a power constraint is assigned, and the available current per gate is much lower than the value which minimizes the propagation delay. The strategy is independent of the process used and is suitable for hand calculations, avoiding the trial-and-error approach based on simulations. Design examples based on a 20 GHz bipolar process are also given.
Alioto, M.B.C., GRASSO A., D., & Palumbo, G. (2006). Design of Cascaded ECL Gates with a Power Constraint. ELECTRONICS LETTERS, 42(4), 211-213 [10.1049/el:20064002].
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11365/3948
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