This paper discusses a general model of Differential Power Analysis (DPA) attacks to static logic circuits. Focusing on symmetric-key cryptographic algorithms, the proposed analysis provides a deeper insight into the vulnerability of cryptographic circuits. The main parameters that are of interest in practical DPA attacks are derived under suitable approximations, and a new figure of merit to measure the DPA effectiveness is proposed. Worst-case conditions under which a cryptographic circuits should be tested to evaluate its robustness against DPA attacks are identified and analyzed. Several interesting properties of DPA attacks are also derived from the proposed model, whose fundamental expressions are compared with the counterparts of the Correlation Power Analysis (CPA) attacks. The model was validated by means of DPA attacks on an FPGA implementation of the Advanced Encryption Standard (AES) algorithm. The experimental results show that the model has a good accuracy, as its error is always lower than 2%.
Scheda prodotto non validato
Scheda prodotto in fase di analisi da parte dello staff di validazione
|Titolo:||A general power model of Differential Power Analysis attacks to static logic circuits|
|Citazione:||Alioto, M.B.C., Poli, M., & Rocchi, S. (2010). A general power model of Differential Power Analysis attacks to static logic circuits. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 18(5), 711-724.|
|Appare nelle tipologie:||1.1 Articolo in rivista|