In this paper, fully digital True Random Bit Generators (TRBGs) targeting area-efficient FPGA implementations are analyzed and evaluated. In this analysis, a very general class of TRBGs is considered that is based on the well-known sampling oscillators used as a building block. A qualitative model is discussed and applied to derive simple design guidelines to implement low-area TRBGs. Extensive measurements are made on TRBGs implemented on Altera Cyclone FPGAs. Results confirm that properly designed TRBGs based on FPGAs can achieve very high-quality random sequences with low area occupation.
Alioto, M.B.C., Fondelli, L., Rocchi, S. (2008). Analysis and performance evaluation of area-efficient true random bit generators on FPGAs. In Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on (pp.1572-1575). New York : IEEE [10.1109/ISCAS.2008.4541732].
Analysis and performance evaluation of area-efficient true random bit generators on FPGAs
ALIOTO, MASSIMO BRUNO CRIS;ROCCHI, SANTINA
2008-01-01
Abstract
In this paper, fully digital True Random Bit Generators (TRBGs) targeting area-efficient FPGA implementations are analyzed and evaluated. In this analysis, a very general class of TRBGs is considered that is based on the well-known sampling oscillators used as a building block. A qualitative model is discussed and applied to derive simple design guidelines to implement low-area TRBGs. Extensive measurements are made on TRBGs implemented on Altera Cyclone FPGAs. Results confirm that properly designed TRBGs based on FPGAs can achieve very high-quality random sequences with low area occupation.
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
https://hdl.handle.net/11365/46677
Attenzione
Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo