In this paper, a strategy to design MOS Current Mode Logic (MCML) tapered buffers is discussed. Closed-form expressions of the speed performance and the power consumption of MCML tapered buffers are first derived. Then, analytical criteria are presented to explore the power-delay design space and properly size the number of stages and the current tapering factor under a speed/power constraint. These criteria incorporate Deep-Sub-Micron (DSM) effects associated with current nanometer technologies from the beginning, and are simple enough to be used in pencil-and-paper calculations. Being general and independent of the process adopted, the proposed design strategy allows for gaining an insight into the interdependence of design parameters, technology parameters and performance. Moreover, the proposed models of the delay/power consumption under assigned constraints allow the designer to predict the achievable performance before actually carrying out the design. Results are validated by means of Spectre simulations on a 90-nm CMOS technology.

Alioto, M.B.C., & G., P. (2008). Power-aware design of nanometer MCML tapered buffers. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS, 55(1), 16-20 [10.1109/TCSII.2007.906983].

Power-aware design of nanometer MCML tapered buffers

ALIOTO, MASSIMO BRUNO CRIS;
2008

Abstract

In this paper, a strategy to design MOS Current Mode Logic (MCML) tapered buffers is discussed. Closed-form expressions of the speed performance and the power consumption of MCML tapered buffers are first derived. Then, analytical criteria are presented to explore the power-delay design space and properly size the number of stages and the current tapering factor under a speed/power constraint. These criteria incorporate Deep-Sub-Micron (DSM) effects associated with current nanometer technologies from the beginning, and are simple enough to be used in pencil-and-paper calculations. Being general and independent of the process adopted, the proposed design strategy allows for gaining an insight into the interdependence of design parameters, technology parameters and performance. Moreover, the proposed models of the delay/power consumption under assigned constraints allow the designer to predict the achievable performance before actually carrying out the design. Results are validated by means of Spectre simulations on a 90-nm CMOS technology.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11365/38924
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