Highly Accurate and Simple Models for CML and ECL gates

In this paper a pencil and paper optimized design for CML and ECL gates are proposed. The approaches are based on simple models which show errors lower than 20% with respect Spice simulations. The optimization is performed in term of bias currents which give the minimum propagation delay, and it is demonstrate that at a price of a 10% propagation delay we can reduce power dissipation of 40%. Moreover, strategies to optimize the transistor area of the CML gates are also included. A comparison between optimized CML and ECL is carried out. It shows the advantage of the CML gate with respect the ECL in term of propagation delay. However, this feature of CML is paid in term of power dissipation. The simple models used and design strategies are validated by using both a traditional and a high-speed bipolar process which have transition frequency equal to 6 GHz and 20 GHz, respectively.