Design Strategies for Source Coupled Logic Gates

In this paper a strategy for the design of Source-Coupled Logic (SCL) gates both with and without an output buffer is proposed. Closed-form design equations to size bias currents and transistors equations to meet assigned specifications are derived from a simple SCL gate analytical delay model, shown to be sufficiently accurate by extensive simulations. The design criteria proposed are simple and provide the designer with a more profound understanding of the trade-off between delay and power consumption. More specifically, design criteria are derived to consciously manage this trade-off in practical design cases, i.e. when either high performance or an optimum balance with power dissipation is needed. Therefore, the strategy proposed is useful right from the early design phases, and avoids tedious simulation iterations.