A simple metric is presented for the accurate prediction of path delay variability during the automated synthesis of digital VLSI circuits. This allows circuit variability to be assessed at early stages within the design process with minimal computational effort, as extensive Monte Carlo or SSTA runs are not required. This paper introduces the metric and investigates its effectiveness. The final predictions of path delay variability are found to be within 10% of measured path delay variability, with an average error of 3%, for a series of test paths synthesised from randomised models of a 130nm technology library. These randomised models are generated from a 3D atomistic simulator and provide more accuracy than traditional Monte Carlo simulation runs.
|Titolo:||Design metrics for RTL level estimation of delay variability due to intradie (random) variations|
|Citazione:||Design metrics for RTL level estimation of delay variability due to intradie (random) variations / Merrett, M.; Wang, Y.; Zwolinski, M.; Maharatna, K.; Alioto, M.. - In: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS PROCEEDINGS. - ISSN 0271-4302. - STAMPA. - (2010), pp. 2498-2501. ((Intervento presentato al convegno 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 tenutosi a Paris (France) nel MAY 30-JUN 02, 2010.|
|Appare nelle tipologie:||4.1 Contributo in Atti di convegno|
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