Positive feedback source-coupled logic (PFSCL) is proposed as an alternative logic style to traditional SCL logic, which is often used in high-resolution mixed-signal integrated circuits. Positive feedback allows for significantly reducing the NMOS transistors' aspect ratio compared to traditional single-ended SCL gates for equal values of design constraints. The resulting reduction in NMOS parasitic capacitances permits a significant speed up, which can be traded off to achieve a power saving for a given speed constraint, as well as a silicon area reduction. PFSCL gates are analytically modeled in terms of their static parameters and delay, which are expressed as a function of bias current, transistors' aspect ratios and process parameters. Spectre simulations by using a 0.35-μm CMOS process confirm that the proposed models are sufficiently accurate in practical cases. PFSCL gates are also compared with traditional SCL circuits by resorting to two different metrics: the gate delay in a Ring Oscillator and that of an inverter with a fan-out of 4. The comparison confirms that PFSCL logic is faster than SCL logic in most cases, and design conditions leading to a speed advantage are identified. As a result, PFSCL gates are an interesting alternative to traditional SCL circuits in mixed-signal applications requiring a high speed or a good balance with power dissipation.
Scheda prodotto non validato
Scheda prodotto in fase di analisi da parte dello staff di validazione
|Titolo:||Modeling and Evaluation of Positive-Feedback Source-Coupled Logic|
|Rivista:||IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS|
|Citazione:||Alioto, M.B.C., Pancioni, L., Rocchi, S., & Vignoli, V. (2004). Modeling and Evaluation of Positive-Feedback Source-Coupled Logic. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS, 51(12), 2345-2355.|
|Appare nelle tipologie:||1.1 Articolo in rivista|