Modeling strategies of the input admittance of RC interconnects for VLSI CAD tools

In this paper, models of the input admittance of RC interconnects are discussed in depth to understand and evaluate their loading effects on the driving CMOS gates. From the detailed analysis of the input admittance pole-zero location, arguments are derived to prove that their input admittance can be accurately approximated to that of a low-order equivalent RC circuit, in contrast to the case of timing analysis of RC wires. More specifically, 1st- or 2nd-order equivalent circuits are derived analytically via the moment matching approach, as opposite to previous analyses that rely on purely numerical approaches. Moreover, simple analytical rules to extend results to arbitrarily complex networks are derived, as opposite to the usual approach that requires the numerical estimation of moments. Being fully analytical, the proposed approach permits to develop models that are extremely simple (i.e., computationally efficient), as well as to gain an insight into the properties of the input admittance of RC interconnects. The proposed equivalent circuits are evaluated and validated in situations that occur in real CAD design flows, where RC wire loading effects are estimated by CAD tools to perform the timing/power analysis of the buffer driving the wire. The analysis is validated through extensive simulations on a 65-nm CMOS technology. Well-defined criteria are also derived to select the appropriate model of the RC wire input admittance for accurate timing/power estimations in VLSI CAD tools.