Correct Procedures to Evaluate the Effect of Intradie Variations on the Delay Variability of Digital Circuits

This paper analyzes Monte Carlo simulation procedures to estimate the impact of process intradie variations on the delay variability of digital circuits. The traditional approach based on the separate evaluation of intradie and interdie variations is shown to be incorrect. Indeed, Monte Carlo simulations on a 65-nm CMOS technology show that this approach can lead to underestimation by up to 35% in the delay variability. Analysis reveals that this error is due to the nonlinear dependence of the parameter of interest (e.g., the delay) on the parameters subject to process variations. Accordingly, a simple simulation strategy is proposed to correctly evaluate the contribution of intradie variations. Results on various Flip-Flop topologies in a 65-nm technology are reported to validate the analysis.