Mixed FBB/RBB: a Novel Low-Leakage Technique for FinFET Forced Stacks

In this paper, a novel technique to reduce the leakage current of FinFET forced stacks under a given delay constraint is presented. This technique takes advantage of the unique feature of four-terminal (4T) FinFETs allowing different transistors to have separately tunable back bias voltages. In this work, a Reverse Back Bias (RBB) voltage is applied to one of the two stacked transistors to reduce its leakage at the cost of a delay penalty, whereas a Forward Back Bias (FBB) voltage is applied to the other one to compensate this delay degradation. The technique is assessed by means of mixed device-circuit simulations for FinFETs that are representative of 40 nm and 27 nm technology generations. Results show that a leakage reduction by up to 50X can be achieved as compared to traditional transistor stacks, while keeping same speed, dynamic energy and sensitivity to process/voltage/temperature variations.