Experimental Study of Leakage-Delay Trade-off in Germanium pMOSFETs for Logic Circuits

In this work we explore the potential of the emerging Germanium technology for logic circuits. We introduce an innovative methodology that extracts the main circuit parameters of interest from experimental measurements on 125 nm high k metal gate Ge pMOSFETs in a Si compatible process flow. Appropriate figures of merit are adopted to highlight the potential of Germanium MOSFETs under realistic VLSI designs that fully exploit system level schemes to minimize leakage (e. g., body biasing, stack forcing). On the one hand, Ge devices outperform Si devices in terms of speed due to the higher hole mobility. On the other hand, the higher off state drain current, evaluated ignoring the junction leakage, in Ge pMOSFETs causes an higher standby power dissipation. We show how this drawback can be alleviated by the application of back biasing and stack effect techniques which are intrinsically more effective in Ge devices. In addition, analysis shows that Ge circuits can actually exhibit a 6.4X lower leakage than Si devices, if the threshold voltage is tuned to match the speed of Si devices.