In this paper a strategy to design high-fan-in multiplexers with minimum delay is proposed. The work extends the optimization proposed in  to the case of switches with driving capability, that exhibit better performance in terms of noise immunity as well as being suitable for voltage scaling, which are becoming increasingly important properties in today’s CMOS technologies. Moreover, the design strategy explicitly accounts for wiring parasitics in design equations. The criteria found are simple and useful right from the early design phases, as well as being independent of the technology used. In addition, an approximate expression of delay is given to predict the speed performance achievable for a given process before actually carrying out the optimized design. As a design example, a 256-input multiplexer was designed and simulated after extracting the parasitics from layout using a 0.35-um CMOS process. The predicted delay agrees well with simulation data.
Alioto, M., Di Cataldo, G., & Palumbo, G. (2002). Optimized design of high fan-in multiplexers using tri-state buffers. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I. FUNDAMENTAL THEORY AND APPLICATIONS, 49(10), 1500-1505.
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|Titolo:||Optimized design of high fan-in multiplexers using tri-state buffers|
|Citazione:||Alioto, M., Di Cataldo, G., & Palumbo, G. (2002). Optimized design of high fan-in multiplexers using tri-state buffers. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I. FUNDAMENTAL THEORY AND APPLICATIONS, 49(10), 1500-1505.|
|Appare nelle tipologie:||1.1 Articolo in rivista|
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