In this paper a strategy to design high-fan-in multiplexers with minimum delay is proposed. The work extends the optimization proposed in [1] to the case of switches with driving capability, that exhibit better performance in terms of noise immunity as well as being suitable for voltage scaling, which are becoming increasingly important properties in today’s CMOS technologies. Moreover, the design strategy explicitly accounts for wiring parasitics in design equations. The criteria found are simple and useful right from the early design phases, as well as being independent of the technology used. In addition, an approximate expression of delay is given to predict the speed performance achievable for a given process before actually carrying out the optimized design. As a design example, a 256-input multiplexer was designed and simulated after extracting the parasitics from layout using a 0.35-um CMOS process. The predicted delay agrees well with simulation data.

Alioto, M., Di Cataldo, G., Palumbo, G. (2002). Optimized design of high fan-in multiplexers using tri-state buffers. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I. FUNDAMENTAL THEORY AND APPLICATIONS, 49(10), 1500-1505 [10.1109/TCSI.2002.803246].

Optimized design of high fan-in multiplexers using tri-state buffers

Alioto, M.;
2002-01-01

Abstract

In this paper a strategy to design high-fan-in multiplexers with minimum delay is proposed. The work extends the optimization proposed in [1] to the case of switches with driving capability, that exhibit better performance in terms of noise immunity as well as being suitable for voltage scaling, which are becoming increasingly important properties in today’s CMOS technologies. Moreover, the design strategy explicitly accounts for wiring parasitics in design equations. The criteria found are simple and useful right from the early design phases, as well as being independent of the technology used. In addition, an approximate expression of delay is given to predict the speed performance achievable for a given process before actually carrying out the optimized design. As a design example, a 256-input multiplexer was designed and simulated after extracting the parasitics from layout using a 0.35-um CMOS process. The predicted delay agrees well with simulation data.
2002
Alioto, M., Di Cataldo, G., Palumbo, G. (2002). Optimized design of high fan-in multiplexers using tri-state buffers. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I. FUNDAMENTAL THEORY AND APPLICATIONS, 49(10), 1500-1505 [10.1109/TCSI.2002.803246].
File in questo prodotto:
File Dimensione Formato  
J10-Optimized Design of High Fan-In Multiplexers using Tri-State Buffers.pdf

non disponibili

Tipologia: PDF editoriale
Licenza: NON PUBBLICO - Accesso privato/ristretto
Dimensione 299.41 kB
Formato Adobe PDF
299.41 kB Adobe PDF   Visualizza/Apri   Richiedi una copia

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11365/38717
 Attenzione

Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo