Positive-Feedback Source-Coupled Logic: a delay model

This paper deals with Positive Feedback Source-Coupled Logic (PFSCL) style, that is obtained by introducing positive feedback in traditional single-ended SCL logic. A delay model of PFSCL gates is derived by properly linearizing the circuit and then simplifying its analysis by eliminating the feedback loop. The analytical expression is simple and suitable for pencil-and-paper calculations. Each delay contribution has an evident meaning, and is thus useful to gain insight into the delay dependence on design and process parameters. The delay model is shown to be accurate enough for practical purposes through Spectre simulations in a wide range of bias, load and design conditions by using a 0.35-μm CMOS process. Performance evaluation of PFSCL gates is carried out by comparison to the traditional SCL logic style. Simulations of a 5-stage ring oscillator in various conditions show that positive feedback allows for a significant speed improvement in several cases.