A circuit approach based on the adoption of mixed dynamic and transmission-gate Full Adder topologies to achieve very fast computation in carry chains is discussed. From a design point of view, the approach is very simple and permits to exceed the speed performance of fast domino logic by more than 30% without degrading the energy efficiency. Post-layout simulations on a 90-nm CMOS technology are presented to validate the results.

Alioto, M.B.C., & G., P. (2007). Very Fast Carry Energy Efficient Computation based on Mixed Dynamic/Transmission-Gate Full Adders. ELECTRONICS LETTERS, 43(13), 707-709.

Very Fast Carry Energy Efficient Computation based on Mixed Dynamic/Transmission-Gate Full Adders

ALIOTO, MASSIMO BRUNO CRIS;
2007

Abstract

A circuit approach based on the adoption of mixed dynamic and transmission-gate Full Adder topologies to achieve very fast computation in carry chains is discussed. From a design point of view, the approach is very simple and permits to exceed the speed performance of fast domino logic by more than 30% without degrading the energy efficiency. Post-layout simulations on a 90-nm CMOS technology are presented to validate the results.
Alioto, M.B.C., & G., P. (2007). Very Fast Carry Energy Efficient Computation based on Mixed Dynamic/Transmission-Gate Full Adders. ELECTRONICS LETTERS, 43(13), 707-709.
File in questo prodotto:
File Dimensione Formato  
J34-Very Fast Carry Energy Efficient Computation based on Mixed DynamicTransmission-Gate Full Adders.pdf

non disponibili

Tipologia: Post-print
Licenza: NON PUBBLICO - Accesso privato/ristretto
Dimensione 73.46 kB
Formato Adobe PDF
73.46 kB Adobe PDF   Visualizza/Apri   Richiedi una copia

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11365/11034
 Attenzione

Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo