A circuit approach based on the adoption of mixed dynamic and transmission-gate Full Adder topologies to achieve very fast computation in carry chains is discussed. From a design point of view, the approach is very simple and permits to exceed the speed performance of fast domino logic by more than 30% without degrading the energy efficiency. Post-layout simulations on a 90-nm CMOS technology are presented to validate the results.
Alioto, M.B.C., G., P. (2007). Very Fast Carry Energy Efficient Computation based on Mixed Dynamic/Transmission-Gate Full Adders. ELECTRONICS LETTERS, 43(13), 707-709.
Very Fast Carry Energy Efficient Computation based on Mixed Dynamic/Transmission-Gate Full Adders
ALIOTO, MASSIMO BRUNO CRIS;
2007-01-01
Abstract
A circuit approach based on the adoption of mixed dynamic and transmission-gate Full Adder topologies to achieve very fast computation in carry chains is discussed. From a design point of view, the approach is very simple and permits to exceed the speed performance of fast domino logic by more than 30% without degrading the energy efficiency. Post-layout simulations on a 90-nm CMOS technology are presented to validate the results.
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https://hdl.handle.net/11365/11034
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