A comprehensive design flow, easy to automate with commercial CAD tools, is presented to optimize nanometer FFs under constraints within the E-D space. By referring to practical design cases, transistor sizing is addressed rigorously. Cases of study for FFs in a 65-nm technology are reported for validation.
Alioto, M.B.C., E., C., G., P. (2010). Nanometer Flip-Flops Design in the E-D Space. In Proc. of ICM 2010 (pp.132-135). New York : IEEE [10.1109/ICM.2010.5696091].
Nanometer Flip-Flops Design in the E-D Space
ALIOTO, MASSIMO BRUNO CRIS;
2010-01-01
Abstract
A comprehensive design flow, easy to automate with commercial CAD tools, is presented to optimize nanometer FFs under constraints within the E-D space. By referring to practical design cases, transistor sizing is addressed rigorously. Cases of study for FFs in a 65-nm technology are reported for validation.
File in questo prodotto:
Non ci sono file associati a questo prodotto.
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
Utilizza questo identificativo per citare o creare un link a questo documento:
https://hdl.handle.net/11365/36172
Attenzione
Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo