A simple procedure to evaluate the energy consumption of adiabatic gate circuits is proposed and validated. The proposed strategy is based on a linearization of the circuit and simplifying the analytical result obtained on the equivalent network. The approach leads to simple relationships which can be used for a pencil-and-paper evaluation or implemented on software. The accuracy of the results is validated by means of Spice simulations on an adiabatic full adder designed with a 0.8 um technology.

Alioto, M.B.C., & Palumbo, G. (2001). Power Estimation in Adiabatic Circuits: A Simple and Accurate Model. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 9(5), 608-615 [10.1109/92.953495].

Power Estimation in Adiabatic Circuits: A Simple and Accurate Model

ALIOTO, MASSIMO BRUNO CRIS;
2001

Abstract

A simple procedure to evaluate the energy consumption of adiabatic gate circuits is proposed and validated. The proposed strategy is based on a linearization of the circuit and simplifying the analytical result obtained on the equivalent network. The approach leads to simple relationships which can be used for a pencil-and-paper evaluation or implemented on software. The accuracy of the results is validated by means of Spice simulations on an adiabatic full adder designed with a 0.8 um technology.
Alioto, M.B.C., & Palumbo, G. (2001). Power Estimation in Adiabatic Circuits: A Simple and Accurate Model. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 9(5), 608-615 [10.1109/92.953495].
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11365/11035
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