In this paper, the effect of process variations on the delay is analyzed in depth for the static and dynamic CMOS logic styles. Analysis allows for gaining an insight into the delay dependence on the fan-in, fan-out and sizing in sub-100 nm technologies. Simple but reasonably accurate models are derived to capture the basic dependencies. The effect of process variations in transistor stacks is analytically modeled and analyzed in detail. The impact of both inter-die and intra-die variations is evaluated and discussed. Interestingly, the input capacitance of static and dynamic logic is shown to be rather insensitive to variations. The delay variability was also shown to be a weak function of the input rise/fall time and load. Analysis shows that Domino logic circuits suffer from a doubled variability, as compared to the static CMOS logic style. The positive feedback associated with the keeper transistor is shown to be responsible for the variability increase, which in turn limits the speed performance. This adds to the well-known speed degradation due to the current contention associated with the keeper transistor. Monte Carlo simulations on a 90-nm technology including layout parasitics are performed to validate the results.
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|Titolo:||Understanding the effect of process variations on the delay of static and domino logic|
|Appare nelle tipologie:||1.1 Articolo in rivista|
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