IRIS
GIORGI, ROBERTO
 Distribuzione geografica
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Continente #
NA - Nord America 11.171
EU - Europa 9.779
AS - Asia 5.787
SA - Sud America 1.014
AF - Africa 281
OC - Oceania 23
Continente sconosciuto - Info sul continente non disponibili 20
Totale 28.075
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Nazione #
US - Stati Uniti d'America 11.012
GB - Regno Unito 2.491
CN - Cina 2.102
RU - Federazione Russa 1.602
SG - Singapore 1.590
IE - Irlanda 1.247
IT - Italia 888
SE - Svezia 883
BR - Brasile 852
UA - Ucraina 831
FR - Francia 708
VN - Vietnam 637
HK - Hong Kong 513
DE - Germania 468
KR - Corea 313
FI - Finlandia 243
ZA - Sudafrica 145
IN - India 135
ES - Italia 123
CA - Canada 74
AR - Argentina 61
BE - Belgio 55
TR - Turchia 53
BD - Bangladesh 52
MX - Messico 51
NL - Olanda 49
IQ - Iraq 48
AE - Emirati Arabi Uniti 47
GR - Grecia 45
JP - Giappone 45
NG - Nigeria 45
PL - Polonia 38
PK - Pakistan 37
ID - Indonesia 27
AT - Austria 25
SA - Arabia Saudita 24
EC - Ecuador 21
AU - Australia 20
CI - Costa d'Avorio 20
EU - Europa 20
HU - Ungheria 19
MY - Malesia 19
UZ - Uzbekistan 19
CL - Cile 18
CO - Colombia 17
IR - Iran 17
VE - Venezuela 17
MA - Marocco 16
PH - Filippine 16
KE - Kenya 14
LT - Lituania 14
NP - Nepal 12
OM - Oman 11
PY - Paraguay 11
RO - Romania 11
IL - Israele 10
JM - Giamaica 10
JO - Giordania 10
TN - Tunisia 10
DZ - Algeria 8
UY - Uruguay 8
DO - Repubblica Dominicana 7
PE - Perù 7
PT - Portogallo 7
CY - Cipro 6
EG - Egitto 6
SN - Senegal 6
DK - Danimarca 5
KZ - Kazakistan 5
LB - Libano 5
NO - Norvegia 5
PA - Panama 5
AZ - Azerbaigian 4
CH - Svizzera 4
QA - Qatar 4
AM - Armenia 3
BH - Bahrain 3
CZ - Repubblica Ceca 3
ET - Etiopia 3
HN - Honduras 3
KW - Kuwait 3
LA - Repubblica Popolare Democratica del Laos 3
TT - Trinidad e Tobago 3
AL - Albania 2
BG - Bulgaria 2
CG - Congo 2
CR - Costa Rica 2
GA - Gabon 2
LK - Sri Lanka 2
LV - Lettonia 2
MD - Moldavia 2
MK - Macedonia 2
NZ - Nuova Zelanda 2
PS - Palestinian Territory 2
TH - Thailandia 2
TW - Taiwan 2
AO - Angola 1
BN - Brunei Darussalam 1
BO - Bolivia 1
BY - Bielorussia 1
Totale 28.057
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Città #
Southend 2.276
Dublin 1.239
Fairfield 1.116
Dallas 933
Singapore 884
Chandler 832
Ashburn 797
Jacksonville 691
Woodbridge 532
Beijing 515
Hong Kong 479
Wilmington 479
Santa Clara 448
Ann Arbor 444
Houston 428
Seattle 421
Moscow 394
Cambridge 374
Siena 357
Hefei 321
Princeton 301
Seoul 295
San Jose 258
Nanjing 248
Ho Chi Minh City 182
The Dalles 177
Los Angeles 164
Hanoi 153
Lauterbourg 147
Johannesburg 131
Dearborn 97
Boardman 96
Buffalo 96
Dong Ket 94
Menlo Park 86
Council Bluffs 85
Milan 81
Nanchang 81
Málaga 74
Helsinki 73
Munich 68
São Paulo 66
San Mateo 59
San Diego 55
Shenyang 53
Atlanta 51
New York 51
Shanghai 50
Brussels 48
Changsha 48
Chicago 44
Rome 44
Tianjin 44
Orem 43
Norwalk 41
Abuja 40
Frankfurt am Main 38
London 37
Hebei 34
Kunming 34
Columbus 33
Haiphong 31
Tokyo 30
Jiaxing 29
Düsseldorf 28
Turku 28
Zhengzhou 27
Hangzhou 26
Jinan 26
Warsaw 26
Guangzhou 25
Redondo Beach 25
Chennai 24
Rio de Janeiro 24
Toronto 24
Florence 23
San Francisco 23
Amsterdam 21
Abidjan 20
Baghdad 20
Bengaluru 20
Boston 20
Porto Alegre 20
Brasília 18
Brooklyn 18
Denver 18
Izmir 18
Phoenix 18
Belo Horizonte 17
Da Nang 17
Falls Church 17
Redmond 17
Redwood City 17
Stockholm 17
Vienna 17
Ningbo 16
Poplar 16
Tashkent 16
Manchester 15
Mumbai 15
Totale 18.687
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Nome #
BlueSign 2 312
AXIOM: A Flexible Platform for the Smart Home 302
A matrix multiplier case study for an evaluation of a configurable Dataflow-Machine 291
Evaluation of a Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Multithreaded Multiprocessors 285
BlueSign Translator 284
A performance evaluation of ARM ISA extension for elliptic curve cryptography over binary finite fields 282
A field experience for a vehicle recognition system using magnetic sensors 282
AXIOM: A Hardware-Software Platform for Cyber Physical Systems 281
A workload characterization of elliptic curve cryptography methods in embedded environments 266
The AXIOM platform for next-generation cyber physical systems 260
Architectural Support for Fault Tolerance in a Teradevice Dataflow System 258
X86_64 vs Aarch64 Performance Validation with COTSon 257
An FPGA-based Scalable Hardware Scheduler for Data-Flow Models 254
Exploiting Locality to Improve Leakage Reduction in Embedded Drowsy I-Caches at Same Area/Speed 254
Guide to DataFlow Supercomputing 253
A Data-Flow Soft-Core Processor for Accelerating Scientific Calculation on FPGAs 253
A Clockless Computing System based on the Static Dataflow Paradigm 251
A scalable thread scheduling co-processor based on data-flow principles 247
A data-flow execution engine for scalable embedded computing 244
Analyzing the Impact of Operating System Activity of different Linux Distributions in a Distributed Environment 240
A design space exploration tool set for future 1K-core high-performance computers 236
DRT: A Lightweight Runtime for Developing Benchmarks for a Dataflow Execution Model 234
AXIOM: a scalable, efficient and reconfigurable embedded platform 232
Making IoT with UDOO 230
A Dynamic Load Balancer for a Cluster of FPGA SoCs 228
AXIOM: A 64-bit reconfigurable hardware/software platform for scalable embedded computing 227
Scalable Embedded Computing through Reconfigurable Hardware: comparing DF-Threads, Cilk, OpenMPI and Jump 226
A fault detection and recovery architecture for a teradevice dataflow system 226
Embedded reconfigurable computing: the ERA approach 222
Reconfigurable Logic Interface Architecture for CPU-FPGA Accelerators 222
A Multi-Pronged Approach to Benchmark Characterization 219
A Novel Architecture and Simulation for Executing Decoupled Threads in Future 1-Kilo-Core Chip 217
Dataflow Support in x86-64 Multicore Architectures through Small Hardware Extensions 214
Exploring future many-core architectures: the TERAFLUX evaluation framework 213
Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise: Designing a Computer Architecture via HLS) 211
Energy Efficiency Exploration on the ZYNQ Ultrascale+ 207
Dynamic Power Reduction in Self-Adaptive Embedded Systems through Benchmark Analysis 205
Rapid Prototyping IoT Solutions Based on Machine Learning 205
An introduction to DF-Threads and their Execution Model 205
Analysis of Sharing Overhead in Shared Memory Multiprocessors 202
Enhancing an x86_64 multi-core architecture with data-flow execution support 202
The AXIOM Project: IoT on Heterogeneous Embedded Platforms 202
MEDEA '08: Proc. 2008 workshop on MEmory performance 200
A Workload Generation Environment for Trace-Driven Simulation of Shared-Bus Multiprocessor 198
The AXIOM project (Agile, eXtensible, fast I/O Module) 198
Embedded reconfigurable architectures 197
Simulation study of memory performance of SMP multiprocessors running a TPC-W workload 194
Instruction Set Extensions for Cryptographic Applications 194
A Data-Flow Methodology for Accelerating FFT 194
Scheduled Dataflow: Execution paradigm, architecture, and performance evaluation 193
Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture 193
Epilogue to [Guide to dataflow supercomputing basic concepts, case studies and a detailed example] 193
From COTSon to HLS: translating timing into an architecture 193
Scalable Embedded Systems: Towards the Convergence of High-Performance and Embedded Computing 192
Postscript to [Guide to DataFlow Supercomputing Basic Concepts, Case Studies, and a Detailed Example] 191
BLUESIGN: traduttore multimediale portatile per non udenti 190
DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems 190
An example application: fourier transform 190
Filtering drowsy instruction cache to achieve better efficiency 189
Tiled Architectures & Recent Proposals for Chip Multiprocessors 188
Architectural Simulation in the Kilo-core Era 186
Integration of simulators in virtual 3D computer science classroom 186
TERAFLUX: Harnessing dataflow in next generation teradevices 185
The AXIOM Software Layers 185
Special Section on Terascale Computing 184
A Case Study on the Design Trade-off of a Thread Level Data Flow based Many-core Architecture 183
A Coherence Protocol for the Elimination of Passive Sharing in Single and Multiple Threaded Shared-Bus Shared-Memory Multiprocessors 183
An Educational Environment for Designing and Performance Tuning of Embedded Systems 181
Trace factory - Generating workloads for trace-driven simulation of shared-bus multiprocessors 178
TERAFLUX: Exploiting Tera-device Computing Challenges 177
Elliptic Curve Cryptography support for ARM based Embedded systems 174
ERA - Embedded Reconfigurable Architectures 173
Final Report and Documentation 173
Dynamically Reconfiguring through Phase Detection on FPGA 172
Modeling Multi-Board Communication in the AXIOM Cyber-Physical System 172
PSCR: A coherence protocol for eliminating passive sharing in shared-bus shared-memory multiprocessors 171
Bridging a Data-Flow Execution Model to a Lightweight Programming Model 171
Cache Memory Design for Embedded Systems Based on Program Locality Analysis 170
Reducing leakage in power-saving capable caches for embedded systems by using a filter cache 170
An Iris+Voice Recognition System for a Smart Doorbell 169
Sistema per la traduzione in Lingua Italiana dei Segni: Blue Sign Translator / Wireless Sign System 168
Exploring Dataflow-based Thread Level Parallelism in Cyber-physical Systems 168
Special track on embedded systems: Applications, solutions, and techniques 168
L'Informatica per i sordi: su palmare la lingua dei segni 167
T-Star (T*): An x86-64 ISA Extension to support thread execution on many cores 167
Fine-tuned TERAFLUX Execution Model 167
The AXIOM Software Layers 166
The TERAFLUX project: Exploiting the dataflow paradigm in next generation teradevices 166
Message from ESA-05 chairs 165
WebRISC-V: A 32/64-bit RISC-V pipeline simulation tool 164
Reducing Leakage through Filter Cache 164
Reducing coherence overhead and boosting performance of high-end SMP multiprocessors running a DSS workload 164
A Soft-IP for Performance Measuring of the Zynq Ultrascale+ CPU/FPGA interface 164
Memory Performance of Public-Key cryptography Methods in Mobile Environments 162
An Educational Environment for Program Behavior Analysis and Cache Memory Design 160
JCacheSim: simulatore visuale di gerarchia di memoria con interprete per programmi MIPS 158
Transactional Memory on a Dataflow Architecture for Accelerating Haskell 158
Using the WebIDE 158
Early results from ERA – Embedded Reconfigurable Architectures 158
A Survey on Real-Time Object Detection on FPGAs 157
Totale 20.430
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Categoria #
all - tutte 82.071
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 82.071
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021602 0 0 0 0 0 0 0 0 0 180 192 230
2021/20222.145 114 232 240 297 101 49 89 65 98 199 186 475
2022/20232.945 206 252 389 463 234 568 53 212 278 108 99 83
2023/20241.659 82 40 106 79 59 401 621 62 5 55 32 117
2024/20253.542 65 201 257 166 375 185 38 300 240 170 378 1.167
2025/20268.026 780 1.220 782 947 1.751 366 1.117 377 342 344 0 0
Totale 28.574