IRIS
GIORGI, ROBERTO
 Distribuzione geografica
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Continente #
NA - Nord America 10.488
EU - Europa 9.404
AS - Asia 4.672
SA - Sud America 913
AF - Africa 90
Continente sconosciuto - Info sul continente non disponibili 20
OC - Oceania 17
Totale 25.604
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Nazione #
US - Stati Uniti d'America 10.366
GB - Regno Unito 2.458
CN - Cina 1.917
RU - Federazione Russa 1.598
SG - Singapore 1.302
IE - Irlanda 1.244
SE - Svezia 879
IT - Italia 855
UA - Ucraina 828
BR - Brasile 801
FR - Francia 526
HK - Hong Kong 423
DE - Germania 420
KR - Corea 300
VN - Vietnam 292
FI - Finlandia 211
ES - Italia 120
IN - India 83
CA - Canada 62
BE - Belgio 55
TR - Turchia 49
AR - Argentina 46
AE - Emirati Arabi Uniti 45
GR - Grecia 44
NL - Olanda 42
BD - Bangladesh 37
MX - Messico 37
JP - Giappone 35
PL - Polonia 33
ZA - Sudafrica 30
IQ - Iraq 27
AT - Austria 23
ID - Indonesia 22
EU - Europa 20
CI - Costa d'Avorio 19
PK - Pakistan 19
SA - Arabia Saudita 17
IR - Iran 16
HU - Ungheria 15
AU - Australia 14
EC - Ecuador 14
UZ - Uzbekistan 14
LT - Lituania 13
CO - Colombia 12
VE - Venezuela 12
MY - Malesia 10
RO - Romania 10
CL - Cile 9
KE - Kenya 9
MA - Marocco 9
IL - Israele 7
JO - Giordania 7
PY - Paraguay 7
TN - Tunisia 7
UY - Uruguay 7
JM - Giamaica 6
OM - Oman 6
CY - Cipro 5
LB - Libano 5
NO - Norvegia 5
NP - Nepal 5
PH - Filippine 5
PT - Portogallo 5
DK - Danimarca 4
DO - Repubblica Dominicana 4
EG - Egitto 4
KZ - Kazakistan 4
PE - Perù 4
SN - Senegal 4
AM - Armenia 3
CH - Svizzera 3
CZ - Repubblica Ceca 3
HN - Honduras 3
LA - Repubblica Popolare Democratica del Laos 3
NG - Nigeria 3
PA - Panama 3
AZ - Azerbaigian 2
CR - Costa Rica 2
ET - Etiopia 2
LK - Sri Lanka 2
MK - Macedonia 2
NZ - Nuova Zelanda 2
QA - Qatar 2
TW - Taiwan 2
AL - Albania 1
BG - Bulgaria 1
BN - Brunei Darussalam 1
CG - Congo 1
DZ - Algeria 1
GA - Gabon 1
GP - Guadalupe 1
GT - Guatemala 1
HR - Croazia 1
IM - Isola di Man 1
KG - Kirghizistan 1
KW - Kuwait 1
LV - Lettonia 1
MD - Moldavia 1
MM - Myanmar 1
MT - Malta 1
Totale 25.596
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Città #
Southend 2.276
Dublin 1.236
Fairfield 1.116
Dallas 931
Chandler 832
Ashburn 750
Singapore 711
Jacksonville 690
Woodbridge 532
Beijing 506
Wilmington 479
Ann Arbor 444
Santa Clara 437
Houston 427
Seattle 421
Hong Kong 411
Moscow 393
Cambridge 374
Siena 357
Princeton 301
Seoul 295
Hefei 263
Nanjing 248
Los Angeles 123
Dearborn 97
Buffalo 96
Boardman 95
Dong Ket 94
Menlo Park 86
Nanchang 81
Milan 75
Málaga 74
Ho Chi Minh City 71
Helsinki 62
São Paulo 62
San Mateo 59
San Diego 55
Shenyang 53
The Dalles 51
Brussels 48
Changsha 48
Council Bluffs 48
Hanoi 48
Atlanta 47
Munich 44
Tianjin 44
Shanghai 43
Norwalk 41
New York 37
Rome 37
Chicago 36
London 35
Hebei 34
Kunming 34
Columbus 33
Jiaxing 29
Düsseldorf 28
Hangzhou 26
Jinan 26
Zhengzhou 26
Redondo Beach 25
Tokyo 25
Warsaw 25
Rio de Janeiro 24
Florence 23
Frankfurt am Main 23
San Francisco 23
Guangzhou 21
Toronto 20
Abidjan 19
Boston 19
Porto Alegre 19
Bengaluru 18
Izmir 18
Johannesburg 18
Belo Horizonte 17
Brasília 17
Brooklyn 17
Falls Church 17
Redmond 17
Redwood City 17
Amsterdam 16
Denver 16
Ningbo 16
Phoenix 16
Vienna 16
Orem 15
Stockholm 15
Chennai 14
Baghdad 13
Poplar 13
Fremont 12
Haiphong 12
Lanzhou 12
Venezia 12
Montreal 11
Tashkent 11
Barcelona 10
Budapest 10
Manchester 10
Totale 17.128
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Nome #
BlueSign 2 288
AXIOM: A Flexible Platform for the Smart Home 283
A matrix multiplier case study for an evaluation of a configurable Dataflow-Machine 275
Evaluation of a Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Multithreaded Multiprocessors 274
A performance evaluation of ARM ISA extension for elliptic curve cryptography over binary finite fields 265
BlueSign Translator 259
A field experience for a vehicle recognition system using magnetic sensors 248
AXIOM: A Hardware-Software Platform for Cyber Physical Systems 247
Architectural Support for Fault Tolerance in a Teradevice Dataflow System 244
A workload characterization of elliptic curve cryptography methods in embedded environments 242
Guide to DataFlow Supercomputing 242
Exploiting Locality to Improve Leakage Reduction in Embedded Drowsy I-Caches at Same Area/Speed 240
The AXIOM platform for next-generation cyber physical systems 240
A Data-Flow Soft-Core Processor for Accelerating Scientific Calculation on FPGAs 234
A Clockless Computing System based on the Static Dataflow Paradigm 232
X86_64 vs Aarch64 Performance Validation with COTSon 228
A scalable thread scheduling co-processor based on data-flow principles 224
An FPGA-based Scalable Hardware Scheduler for Data-Flow Models 224
Analyzing the Impact of Operating System Activity of different Linux Distributions in a Distributed Environment 223
A design space exploration tool set for future 1K-core high-performance computers 222
Making IoT with UDOO 218
AXIOM: a scalable, efficient and reconfigurable embedded platform 218
AXIOM: A 64-bit reconfigurable hardware/software platform for scalable embedded computing 218
DRT: A Lightweight Runtime for Developing Benchmarks for a Dataflow Execution Model 218
A data-flow execution engine for scalable embedded computing 215
A fault detection and recovery architecture for a teradevice dataflow system 213
Scalable Embedded Computing through Reconfigurable Hardware: comparing DF-Threads, Cilk, OpenMPI and Jump 212
Embedded reconfigurable computing: the ERA approach 204
A Dynamic Load Balancer for a Cluster of FPGA SoCs 204
A Novel Architecture and Simulation for Executing Decoupled Threads in Future 1-Kilo-Core Chip 202
A Multi-Pronged Approach to Benchmark Characterization 200
Dataflow Support in x86-64 Multicore Architectures through Small Hardware Extensions 199
Dynamic Power Reduction in Self-Adaptive Embedded Systems through Benchmark Analysis 198
Exploring future many-core architectures: the TERAFLUX evaluation framework 197
Rapid Prototyping IoT Solutions Based on Machine Learning 196
Enhancing an x86_64 multi-core architecture with data-flow execution support 196
Energy Efficiency Exploration on the ZYNQ Ultrascale+ 195
MEDEA '08: Proc. 2008 workshop on MEmory performance 194
Reconfigurable Logic Interface Architecture for CPU-FPGA Accelerators 194
Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise: Designing a Computer Architecture via HLS) 193
An introduction to DF-Threads and their Execution Model 192
Simulation study of memory performance of SMP multiprocessors running a TPC-W workload 187
Embedded reconfigurable architectures 185
The AXIOM Project: IoT on Heterogeneous Embedded Platforms 184
Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture 183
Scheduled Dataflow: Execution paradigm, architecture, and performance evaluation 181
Filtering drowsy instruction cache to achieve better efficiency 180
Analysis of Sharing Overhead in Shared Memory Multiprocessors 179
Postscript to [Guide to DataFlow Supercomputing Basic Concepts, Case Studies, and a Detailed Example] 179
TERAFLUX: Harnessing dataflow in next generation teradevices 179
A Workload Generation Environment for Trace-Driven Simulation of Shared-Bus Multiprocessor 179
Instruction Set Extensions for Cryptographic Applications 177
An example application: fourier transform 176
The AXIOM Software Layers 176
Special Section on Terascale Computing 175
The AXIOM project (Agile, eXtensible, fast I/O Module) 174
A Data-Flow Methodology for Accelerating FFT 174
BLUESIGN: traduttore multimediale portatile per non udenti 173
Architectural Simulation in the Kilo-core Era 172
Trace factory - Generating workloads for trace-driven simulation of shared-bus multiprocessors 170
Epilogue to [Guide to dataflow supercomputing basic concepts, case studies and a detailed example] 169
Scalable Embedded Systems: Towards the Convergence of High-Performance and Embedded Computing 169
From COTSon to HLS: translating timing into an architecture 169
An Educational Environment for Designing and Performance Tuning of Embedded Systems 168
ERA - Embedded Reconfigurable Architectures 167
TERAFLUX: Exploiting Tera-device Computing Challenges 167
DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems 166
A Coherence Protocol for the Elimination of Passive Sharing in Single and Multiple Threaded Shared-Bus Shared-Memory Multiprocessors 166
Final Report and Documentation 164
Integration of simulators in virtual 3D computer science classroom 164
PSCR: A coherence protocol for eliminating passive sharing in shared-bus shared-memory multiprocessors 163
Tiled Architectures & Recent Proposals for Chip Multiprocessors 163
Exploring Dataflow-based Thread Level Parallelism in Cyber-physical Systems 163
A Case Study on the Design Trade-off of a Thread Level Data Flow based Many-core Architecture 162
Bridging a Data-Flow Execution Model to a Lightweight Programming Model 162
Modeling Multi-Board Communication in the AXIOM Cyber-Physical System 161
Dynamically Reconfiguring through Phase Detection on FPGA 160
Special track on embedded systems: Applications, solutions, and techniques 159
The TERAFLUX project: Exploiting the dataflow paradigm in next generation teradevices 159
Reducing Leakage through Filter Cache 158
L'Informatica per i sordi: su palmare la lingua dei segni 157
Reducing leakage in power-saving capable caches for embedded systems by using a filter cache 157
Sistema per la traduzione in Lingua Italiana dei Segni: Blue Sign Translator / Wireless Sign System 156
Elliptic Curve Cryptography support for ARM based Embedded systems 154
An Iris+Voice Recognition System for a Smart Doorbell 154
Fine-tuned TERAFLUX Execution Model 153
Proceedings of the 2006 workshop on MEmory performance: DEaling with Applications, systems and architectures 152
Message from ESA-05 chairs 152
Cache Memory Design for Embedded Systems Based on Program Locality Analysis 151
The AXIOM Software Layers 151
Using the WebIDE 151
Early results from ERA – Embedded Reconfigurable Architectures 149
Simulating a Multi-core x86_64 Architecture with Hardware ISA Extension Supporting a Data-Flow Execution Model 148
Reducing coherence overhead and boosting performance of high-end SMP multiprocessors running a DSS workload 148
Analyzing Scalability of Deblocking Filter of H.264 via TLP Exploitation in a New Many-Core Architecture 148
An Educational Environment for Program Behavior Analysis and Cache Memory Design 147
Memory Performance of Public-Key cryptography Methods in Mobile Environments 147
A Soft-IP for Performance Measuring of the Zynq Ultrascale+ CPU/FPGA interface 145
T-Star (T*): An x86-64 ISA Extension to support thread execution on many cores 144
Programming Abstractions and Toolchain for Dataflow Multithreading Architectures 143
Totale 18.879
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Categoria #
all - tutte 77.148
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 77.148
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/20211.632 0 0 0 0 0 296 114 390 230 180 192 230
2021/20222.145 114 232 240 297 101 49 89 65 98 199 186 475
2022/20232.945 206 252 389 463 234 568 53 212 278 108 99 83
2023/20241.659 82 40 106 79 59 401 621 62 5 55 32 117
2024/20253.542 65 201 257 166 375 185 38 300 240 170 378 1.167
2025/20265.555 780 1.220 782 947 1.751 75 0 0 0 0 0 0
Totale 26.103