T-Star (T*) is an ISA-extension that supports a promising execution model to exploit Thread Level Parallelism (TLP) in designing for the next generation chip. This model relies on DataFlow principles. A compiler partitions the program into non-blocking threads which start consuming their own data frames when all their inputs become ready. Especially for future systems composed of thousands of cores on a single chip, we believe that this model is very efficient because it allows less synchronization delays among parallel threads. In this paper we describe some initial works towards simulating 1 kilo-core DataFlow enable chips.
Ho, N., PORTERO TRUJILLO, A., Scionti, A., Giorgi, R. (2012). A Novel Architecture and Simulation for Executing Decoupled Threads in Future 1-Kilo-Core Chip. In HiPEAC ACACES-2012 (pp. 83-86). Fiuggi, Italy.
A Novel Architecture and Simulation for Executing Decoupled Threads in Future 1-Kilo-Core Chip
HO, NAM;PORTERO TRUJILLO, ANTONIO;SCIONTI, ALBERTO;GIORGI, ROBERTO
2012-01-01
Abstract
T-Star (T*) is an ISA-extension that supports a promising execution model to exploit Thread Level Parallelism (TLP) in designing for the next generation chip. This model relies on DataFlow principles. A compiler partitions the program into non-blocking threads which start consuming their own data frames when all their inputs become ready. Especially for future systems composed of thousands of cores on a single chip, we believe that this model is very efficient because it allows less synchronization delays among parallel threads. In this paper we describe some initial works towards simulating 1 kilo-core DataFlow enable chips.
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https://hdl.handle.net/11365/35554
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