FPGA MPSoC platforms are widely known for their advantages of reconfigurability, highperformance, and power efficiency especially in domain-specific architectures over general processors. In these platforms, one of the key performance metrics is the data throughput between the processing system (PS) and the programmable logic (PL) parts, particularly when it comes to offload a computationally intensive workload to the PL. This paper presents a soft-IP and its needed software to evaluate the performance of the data transfer by AXI-Lite interface between PS and PL of the Xilinx Zynq Ultrascale+. For that goal, we use an AXI-Lite register based interface between the PS and the PL and a CRC16 engine implemented on the PL in order to validate the correctness of the received data packets and find the maximum achievable throughput from the PS, while the software is running on Linux Ubuntu.
Khalili Maybodi, F., & Giorgi, R. (2019). A Soft-IP for Performance Measuring of the Zynq Ultrascale+ CPU/FPGA interface, 5-8.
|Titolo:||A Soft-IP for Performance Measuring of the Zynq Ultrascale+ CPU/FPGA interface|
KHALILI MAYBODI, FARNAM (Corresponding)
GIORGI, ROBERTO [Supervision] (Corresponding)
|Citazione:||Khalili Maybodi, F., & Giorgi, R. (2019). A Soft-IP for Performance Measuring of the Zynq Ultrascale+ CPU/FPGA interface, 5-8.|
|Appare nelle tipologie:||4.3 Poster|