The number of cores per chip keeps increasing in order to improve performance while controlling the power. According to semiconductor roadmaps, future computing systems will reach the scale of 1 Tera devices in a single package and therefore many-core (e.g. 1000 or more) will be the norm. Here, we describe an ISE (ISA Extension) that we are experimenting in the x86-64 ISA in order to provide an efficient, fast support for fine-grained threads. The new ISE enables a different execution model based on the availability of data and opens the doors for many architectural optimizations not possible in current cores. We also describe the architectural support related to the T* extension.
Antoni, P., Zhibin, Y.u., Giorgi, R. (2011). T-Star (T*): An x86-64 ISA Extension to support thread execution on many cores. In Proceedings of HiPEAC ACACES-2011 (pp.277-280).
T-Star (T*): An x86-64 ISA Extension to support thread execution on many cores
GIORGI, ROBERTO
2011-01-01
Abstract
The number of cores per chip keeps increasing in order to improve performance while controlling the power. According to semiconductor roadmaps, future computing systems will reach the scale of 1 Tera devices in a single package and therefore many-core (e.g. 1000 or more) will be the norm. Here, we describe an ISE (ISA Extension) that we are experimenting in the x86-64 ISA in order to provide an efficient, fast support for fine-grained threads. The new ISE enables a different execution model based on the availability of data and opens the doors for many architectural optimizations not possible in current cores. We also describe the architectural support related to the T* extension.
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https://hdl.handle.net/11365/46805
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