Leakage power in data cache memories represents a sizable fraction of total power consumption, and many techniques have been proposed to reduce it. As a matter of fact, during a fixed period of time, only a small subset of cache lines is used. Previous techniques put unused lines, for example, to drowsy state or switch them off completely (cache decay) in order to save power. Our idea is to adaptively select mostly used cache lines. We found that this can be achieved automatically by using a tiny cache acting as a filter L0 cache. Our main contributions are: i) evaluation of filter cache to reduce leakage; ii) improvement of other existing power-saving techniques; iii) providing results to select the most promising solution. Our experiments, with complete MiBench suite for ARM based processor, show (in average) 10% improvement in leakage saving and 17% in leakage energy-delay versus drowsy-cache; versus decay-cache we found 6% improvement in leakage saving and 13% in leakage energy-delay.

Giorgi, R., P., B. (2007). Reducing leakage in power-saving capable caches for embedded systems by using a filter cache. In Proceedings of the MEDEA 2007 Worskhop on Memory Performance: Dealing with Applications, Systems and (pp.97-104). ACM [10.1145/1327171.1327183].

Reducing leakage in power-saving capable caches for embedded systems by using a filter cache

GIORGI, ROBERTO;
2007-01-01

Abstract

Leakage power in data cache memories represents a sizable fraction of total power consumption, and many techniques have been proposed to reduce it. As a matter of fact, during a fixed period of time, only a small subset of cache lines is used. Previous techniques put unused lines, for example, to drowsy state or switch them off completely (cache decay) in order to save power. Our idea is to adaptively select mostly used cache lines. We found that this can be achieved automatically by using a tiny cache acting as a filter L0 cache. Our main contributions are: i) evaluation of filter cache to reduce leakage; ii) improvement of other existing power-saving techniques; iii) providing results to select the most promising solution. Our experiments, with complete MiBench suite for ARM based processor, show (in average) 10% improvement in leakage saving and 17% in leakage energy-delay versus drowsy-cache; versus decay-cache we found 6% improvement in leakage saving and 13% in leakage energy-delay.
2007
9781595938077
Giorgi, R., P., B. (2007). Reducing leakage in power-saving capable caches for embedded systems by using a filter cache. In Proceedings of the MEDEA 2007 Worskhop on Memory Performance: Dealing with Applications, Systems and (pp.97-104). ACM [10.1145/1327171.1327183].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11365/46856
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