| Nome |
# |
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A Data-Flow Soft-Core Processor for Accelerating Scientific Calculation on FPGAs, file e0feeaa6-0935-44d2-e053-6605fe0a8db0
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152
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Special Section on Terascale Computing, file e0feeaa9-54b2-44d2-e053-6605fe0a8db0
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124
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The AXIOM Software Layers, file e0feeaa6-0859-44d2-e053-6605fe0a8db0
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121
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Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise: Designing a Computer
Architecture via HLS), file e0feeaa8-3ff2-44d2-e053-6605fe0a8db0
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117
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WebRISC-V: A 32/64-bit RISC-V pipeline simulation tool, file 6993e345-6a1a-4a1c-9a79-9282281451e1
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106
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Reconfigurable Logic Interface Architecture for CPU-FPGA Accelerators, file e0feeaa7-f076-44d2-e053-6605fe0a8db0
|
75
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X86_64 vs Aarch64 Performance Validation with COTSon, file e0feeaa8-3875-44d2-e053-6605fe0a8db0
|
70
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WebRISC-V: A RISC-V Educational Simulator featuring RV64IM, Pipeline and Web-Based UI, file e0feeaaa-3db2-44d2-e053-6605fe0a8db0
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59
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Accelerating Haskell on a Dataflow Architecture: a case study including Transactional Memory, file e0feeaa9-3a62-44d2-e053-6605fe0a8db0
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58
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WebRISC-V: a Web-Based Education-Oriented RISC-V Pipeline Simulation Environment, file e0feeaaa-3877-44d2-e053-6605fe0a8db0
|
58
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Making IoT with UDOO, file e0feeaa9-3037-44d2-e053-6605fe0a8db0
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54
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A data-flow execution engine for scalable embedded computing, file e0feeaa7-c918-44d2-e053-6605fe0a8db0
|
39
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An Extended Tracing System for the COTSon Simulator, file e0feeaaa-3879-44d2-e053-6605fe0a8db0
|
38
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An FPGA-based Scalable Hardware Scheduler for Data-Flow Models, file e0feeaa7-c74a-44d2-e053-6605fe0a8db0
|
37
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A Dynamic Load Balancer for a Cluster of FPGA SoCs, file e0feeaaa-240a-44d2-e053-6605fe0a8db0
|
33
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Simulating next-generation Cyber-physical computing platforms, file e0feeaa9-84d7-44d2-e053-6605fe0a8db0
|
30
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A Soft-IP for Performance Measuring of the Zynq Ultrascale+ CPU/FPGA interface, file e0feeaaa-6787-44d2-e053-6605fe0a8db0
|
29
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From COTSon to HLS: translating timing into an architecture, file e0feeaa7-ea92-44d2-e053-6605fe0a8db0
|
28
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Transactional Memory on a Dataflow Architecture for Accelerating Haskell, file e0feeaa9-2c8b-44d2-e053-6605fe0a8db0
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22
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Distributed large-scale graph processing on FPGAs, file 37219f75-899d-4629-b787-a884c221ec7f
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11
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DRT: A Lightweight Runtime for Developing Benchmarks for a Dataflow Execution Model, file e0feeaaa-6d6f-44d2-e053-6605fe0a8db0
|
6
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Evaluation of a Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Multithreaded Multiprocessors, file e0feeaa4-c005-44d2-e053-6605fe0a8db0
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4
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A workload characterization of elliptic curve cryptography methods in embedded environments, file e0feeaa4-de39-44d2-e053-6605fe0a8db0
|
4
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An Educational Environment for Designing and Performance Tuning of Embedded Systems, file e0feeaa8-b19e-44d2-e053-6605fe0a8db0
|
4
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Effects of instruction-set extensions on an embedded processor: A case study on elliptic-curve cryptography over GF(2(m)), file e0feeaa4-e2c1-44d2-e053-6605fe0a8db0
|
3
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A performance evaluation of ARM ISA extension for elliptic curve cryptography over binary finite fields, file e0feeaa4-dd01-44d2-e053-6605fe0a8db0
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2
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A design space exploration tool set for future 1K-core high-performance computers, file e0feeaa7-ea90-44d2-e053-6605fe0a8db0
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2
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A scalable thread scheduling co-processor based on data-flow principles, file e0feeaa9-028d-44d2-e053-6605fe0a8db0
|
2
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AXIOM: A 64-bit reconfigurable hardware/software platform for scalable embedded computing, file e0feeaa9-7701-44d2-e053-6605fe0a8db0
|
2
|
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Scalable Embedded Systems: Towards the Convergence of High-Performance and Embedded Computing, file e0feeaa9-8959-44d2-e053-6605fe0a8db0
|
2
|
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Exploring Dataflow-based Thread Level Parallelism in Cyber-physical Systems, file e0feeaa9-895a-44d2-e053-6605fe0a8db0
|
2
|
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A Data-Flow Methodology for Accelerating FFT, file e0feeaaa-1bda-44d2-e053-6605fe0a8db0
|
2
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An Iris+Voice Recognition System for a Smart Doorbell, file e0feeaaa-3db6-44d2-e053-6605fe0a8db0
|
2
|
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Simulation study of memory performance of SMP multiprocessors running a TPC-W workload, file e0feeaa4-c295-44d2-e053-6605fe0a8db0
|
1
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L'Informatica per i sordi: su palmare la lingua dei segni, file e0feeaa4-c38a-44d2-e053-6605fe0a8db0
|
1
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Instruction Set Extensions for Cryptographic Applications, file e0feeaa4-e1cd-44d2-e053-6605fe0a8db0
|
1
|
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TERAFLUX: Exploiting Tera-device Computing Challenges, file e0feeaa4-ee7e-44d2-e053-6605fe0a8db0
|
1
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Exploring future many-core architectures: the TERAFLUX evaluation framework, file e0feeaa6-c116-44d2-e053-6605fe0a8db0
|
1
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The AXIOM platform for next-generation cyber physical systems, file e0feeaa6-ce6b-44d2-e053-6605fe0a8db0
|
1
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Energy Efficiency Exploration on the ZYNQ Ultrascale+, file e0feeaa7-f3fd-44d2-e053-6605fe0a8db0
|
1
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Architectural Support for Fault Tolerance in a Teradevice Dataflow System, file e0feeaa9-1a8a-44d2-e053-6605fe0a8db0
|
1
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The AXIOM project (Agile, eXtensible, fast I/O Module), file e0feeaa9-26d0-44d2-e053-6605fe0a8db0
|
1
|
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Dataflow Support in x86-64 Multicore Architectures through Small Hardware Extensions, file e0feeaa9-702a-44d2-e053-6605fe0a8db0
|
1
|
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AXIOM: A Hardware-Software Platform for Cyber Physical Systems, file e0feeaa9-7c3a-44d2-e053-6605fe0a8db0
|
1
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Dynamic Power Reduction in Self-Adaptive Embedded Systems through Benchmark Analysis, file e0feeaaa-3c73-44d2-e053-6605fe0a8db0
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1
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The Italian research on HPC key technologies across EuroHPC, file e0feeaaa-3db4-44d2-e053-6605fe0a8db0
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1
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Embedded Face Analysis for Smart Videosurveillance, file e0feeaaa-3db7-44d2-e053-6605fe0a8db0
|
1
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Analyzing the Impact of Operating System Activity of different Linux Distributions in a Distributed Environment, file e0feeaaa-460e-44d2-e053-6605fe0a8db0
|
1
|
| Totale |
1.313 |