Nowadays, the increasing core number benefits many workloads, but programming limitations to exploiting full performance still remain. A Data-Flow execution model is capable of taking advantage of the full parallelism offered by multicore systems. In such model, the execution can be decomposed in fine-grain threads named Data-Flow Threads (DF-Threads) so that each of them can execute only when their inputs are available. The execution overhead and power consumption is lowered thanks to the reduction of the data push-pull, as well as the burden of thread management.

Giorgi, R., KHALILI MAYBODI, F., Procaccini, M. (2018). From COTSon to HLS: translating timing into an architecture.

From COTSon to HLS: translating timing into an architecture

Roberto Giorgi;Farnam Khalili;Marco Procaccini
2018-01-01

Abstract

Nowadays, the increasing core number benefits many workloads, but programming limitations to exploiting full performance still remain. A Data-Flow execution model is capable of taking advantage of the full parallelism offered by multicore systems. In such model, the execution can be decomposed in fine-grain threads named Data-Flow Threads (DF-Threads) so that each of them can execute only when their inputs are available. The execution overhead and power consumption is lowered thanks to the reduction of the data push-pull, as well as the burden of thread management.
Giorgi, R., KHALILI MAYBODI, F., Procaccini, M. (2018). From COTSon to HLS: translating timing into an architecture.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11365/1069314