KHALILI MAYBODI, FARNAM
 Distribuzione geografica
Continente #
NA - Nord America 531
EU - Europa 504
AS - Asia 133
OC - Oceania 1
SA - Sud America 1
Totale 1.170
Nazione #
US - Stati Uniti d'America 531
GB - Regno Unito 117
IE - Irlanda 116
IT - Italia 91
CN - Cina 76
SE - Svezia 74
FR - Francia 38
VN - Vietnam 34
UA - Ucraina 20
ES - Italia 10
DE - Germania 9
FI - Finlandia 9
AT - Austria 7
BE - Belgio 7
SG - Singapore 7
IN - India 6
IR - Iran 4
TR - Turchia 3
HU - Ungheria 2
RU - Federazione Russa 2
AU - Australia 1
BR - Brasile 1
DK - Danimarca 1
HK - Hong Kong 1
PT - Portogallo 1
SA - Arabia Saudita 1
TH - Thailandia 1
Totale 1.170
Città #
Dublin 116
Southend 109
Chandler 98
Fairfield 66
Siena 65
Ashburn 48
Ann Arbor 42
Dong Ket 34
Woodbridge 30
Beijing 27
Houston 25
Jacksonville 25
Dearborn 23
Cambridge 22
Seattle 20
Wilmington 20
Princeton 13
Málaga 10
Helsinki 9
Nanjing 9
Florence 8
Brussels 7
Vienna 7
Shenyang 6
Changsha 5
Boardman 4
Madison 4
Shanghai 4
Singapore 4
Zhengzhou 4
Fremont 3
Jinan 3
Kunming 3
San Mateo 3
Bengaluru 2
Budapest 2
Castelfranco Emilia 2
Edinburgh 2
Fuzhou 2
Izmir 2
Jiaxing 2
Norwalk 2
Pune 2
Rome 2
San Diego 2
Wuhan 2
Zanjan 2
Acton 1
Augusta 1
Baoding 1
Bonndorf 1
Braunschweig 1
Chennai 1
Empoli 1
Enfield 1
Genoa 1
Hebei 1
Hefei 1
Hellerup 1
Lanzhou 1
Lisbon 1
London 1
Los Angeles 1
Milan 1
Mitcham 1
Moscow 1
Munich 1
Nanchang 1
Nashville 1
Newark 1
Ningbo 1
Papenburg 1
Paris 1
Pisa 1
Redwood City 1
Riyadh 1
Sydney 1
Terranuova Bracciolini 1
Tianjin 1
Trieste 1
Yurovka 1
Totale 936
Nome #
Analyzing the Impact of Operating System Activity of different Linux Distributions in a Distributed Environment 169
A design space exploration tool set for future 1K-core high-performance computers 154
AXIOM: a scalable, efficient and reconfigurable embedded platform 151
Energy Efficiency Exploration on the ZYNQ Ultrascale+ 129
Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise: Designing a Computer Architecture via HLS) 129
An FPGA-based Scalable Hardware Scheduler for Data-Flow Models 128
Reconfigurable Logic Interface Architecture for CPU-FPGA Accelerators 119
From COTSon to HLS: translating timing into an architecture 115
A Dynamic Load Balancer for a Cluster of FPGA SoCs 103
A Soft-IP for Performance Measuring of the Zynq Ultrascale+ CPU/FPGA interface 76
Totale 1.273
Categoria #
all - tutte 3.613
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 3.613


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/2020288 33 9 9 36 23 27 31 32 28 27 11 22
2020/2021165 5 14 1 20 8 19 8 25 2 11 10 42
2021/2022200 8 13 55 8 21 0 9 6 12 16 27 25
2022/2023275 21 42 20 40 10 45 11 27 25 19 12 3
2023/2024168 3 3 9 12 8 31 77 12 2 4 1 6
2024/20255 5 0 0 0 0 0 0 0 0 0 0 0
Totale 1.273