Digital Nonlinear Oscillators: A Novel Class of Circuits for the Design of Entropy Sources in Programmable Logic Devices

In recent years, cybersecurity is gaining more and more importance. Cryptography is used in numerous applications, such as authentication and encryption of data in communications, access control to restricted or protected areas, electronic payments. It is safe to assume that the presence of cryptographic systems in future technologies will become increasingly pervasive, leading to a greater demand for energy efficiency, hardware reliability, integration, portability, and security. However, this pervasiveness introduces new challenges: the implementation of conventional cryptographic standards approved by NIST requires the achievement of performance in terms of timing, chip area, power and resource consumption that are not compatible with reduced complexity hardware devices, such as IoT systems. In response to this limitation, lightweight cryptography comes into play - a branch of cryptography that provides tailor-made solutions for resource-limited devices. One of the fundamental classes of cryptographic hardware primitives is represented by Random Number Generators (RNGs), that is, systems that provide sequences of integers that are supposed to be unpredictable. The circuits and systems that implement RNGs can be divided into two categories, namely Pseudo Random Number Generators (PRNGs) and True Random Number Generators (TRNGs). PRNGs are deterministic and possibly periodic finite state machines, capable of generating sequences that appear to be random. In other words, a PRNG is a device that generates and repeats a finite random sequence, saved in memory, or generated by calculation. A TRNG, on the other hand, is a device that generates random numbers based on real stochastic physical processes. Typically, a hardware TRNG consists of a mixed-signal circuit that is classified according to the stochastic process on which it is based. Specifically, the most used sources of randomness are chaotic circuits, high jitter oscillators, circuits that measure other stochastic processes. A chaotic circuit is an analog or mixed-signal circuit in which currents and voltages vary over time based on certain mathematical properties. The evolution over time of these currents and voltages can be interpreted as the evolution of the state of a chaotic nonlinear dynamical system. Jitter noise can instead be defined as the deviation of the output signal of an oscillator from its true periodicity, which causes uncertainty in its low-high and high-low transition times. Other possible stochastic processes that a TRNG can use may involve radioactive decay, photon detection, or electronic noise in semiconductor devices. TRNG proposals presented in the literature are typically designed in the form of Application Specific Integrated Circuits (ASICs). On the other hand, in recent years more and more researchers are exploring the possibility of designing TRNGs in Programmable Logic Devices (PLDs). A PLD offers, compared to an ASIC, clear advantages in terms of cost and versatility. At the same time, however, there is currently a widespread lack of trust in these PLD-based architectures, particularly due to strong cryptographic weaknesses found in Ring Oscillator-based solutions. The goal of this thesis is to show how this mistrust does not depend on poor performance in cryptographic terms of solutions for the generation of random numbers based on programmable digital technologies, but rather on a still immature approach in the study of TRNG architectures designed on PLDs. During the thesis chapters a new class of nonlinear circuits based on digital hardware is introduced that can be used as entropy sources for TRNGs implemented in PLDs, identified by the denomination of Digital Nonlinear Oscillators (DNOs). In Chapter 2 a novel class of circuits that can be used to design entropy sources for True Random Number Generation, called Digital Nonlinear Oscillators (DNOs), is introduced. DNOs constitute nonlinear dynamical systems capable of supporting complex dynamics in the time-continuous domain, although they are based on purely digital hardware. By virtue of this characteristic, these circuits are suitable for their implementation on Programmable Logic Devices. By focusing the analysis on Digital Nonlinear Oscillators implemented in FPGAs, a preliminary comparison is proposed between three different circuit topologies referable to the introduced class, to demonstrate how circuits of this type can have different characteristics, depending on their dynamical behavior and the hardware implementation. In Chapter 3 a methodology for the analysis and design of Digital Nonlinear Oscillators based on the evaluation of their electronics aspects, their dynamical behavior, and the information they can generate is formalized. The presented methodology makes use of different tools, such as figures of merit, simplified dynamical models, advanced numerical simulations and experimental tests carried out through implementation on FPGA. Each of these tools is analyzed both in its theoretical premises and through explanatory examples. In Chapter 4 the analysis and design methodologies of Digital Nonlinear Oscillators formalized in Chapter 3 are used to describe the complete workflow followed for the design of a novel DNO topology. This DNO is characterized by chaotic dynamical behaviors and can achieve high performance in terms of generated entropy, downstream of a reduced hardware complexity and high sampling frequencies. By exploiting the simplified dynamical model, the advanced numerical simulations in Cadence Virtuoso and the FPGA implementation, the presented topology is extensively analyzed both from a theoretical point of view (notable circuit sub-elements that make up the topology, bifurcation diagrams, internal periodicities) and from an experimental point of view (generated entropy, source autocorrelation, sensitivity to routing, application of standard statistical tests). In Chapter 5 an algorithm, called Maximum Worst-Case Entropy Selector (MWCES), that aims to identify, within a set of entropy sources, which offers the best performance in terms of worst-case entropy, also known in literature as "min-entropy", is presented. This algorithm is designed to be implemented in low-complexity digital architectures, suitable for lightweight cryptographic applications, thus allowing online maximization of the performance of a random number generation system based on Digital Nonlinear Oscillators. This chapter presents the theoretical premises underlying the algorithm formulation, some notable examples of its generic application and, finally, considerations related to its hardware implementation in FPGA.