Sfoglia per Autore
Distributed large-scale graph processing on FPGAs
2023-01-01 Sahebi, Amin; Barbone, Marco; Procaccini, Marco; Luk, Wayne; Gaydadjiev, Georgi; Giorgi, Roberto
WebRISC-V: A 32/64-bit RISC-V pipeline simulation tool
2022-01-01 Mariotti, G.; Giorgi, R.
The Italian research on HPC key technologies across EuroHPC
2021-01-01 Aldinucci, M.; Agosta, G.; Andreini, A.; Ardagna, C. A.; Bartolini, A.; Cilardo, A.; Cosenza, B.; Danelutto, M.; Esposito, R.; Fornaciari, W.; Giorgi, R.; Lengani, D.; Montella, R.; Olivieri, M.; Saponara, S.; Simoni, D.; Torquati, M.
DRT: A Lightweight Runtime for Developing Benchmarks for a Dataflow Execution Model
2021-01-01 Giorgi, Roberto; Sahebi, Amin; Procaccini, Marco
The AXIOM Project: IoT on Heterogeneous Embedded Platforms
2021-01-01 Filgueras, Antonio; Vidal, Miquel; Mateu, Marc; Jimenez-Gonzalez, Daniel; Alvarez, Carlos; Martorell, Xavier; Ayguade', Eduard; Theodoropoulos, Dimitrios; Pnevmatikatos, Dionisios; Gai, Paolo; Garzarella, Stefano; Oro, David; Hernando, Javier; Bettin, Nicola; Pomella, Alberto; Procaccini, Marco; Giorgi, Roberto
An Extended Tracing System for the COTSon Simulator
2020-01-01 Procaccini, Marco; Giorgi, Roberto
WebRISC-V: A RISC-V Educational Simulator featuring RV64IM, Pipeline and Web-Based UI
2020-01-01 Giorgi, Roberto; Mariotti, Gianfranco
A Dynamic Load Balancer for a Cluster of FPGA SoCs
2020-01-01 KHALILI MAYBODI, Farnam; Giorgi, Roberto
X86_64 vs Aarch64 Performance Validation with COTSon
2019-01-01 Giorgi, Roberto; Procaccini, Marco
Analyzing the Impact of Operating System Activity of different Linux Distributions in a Distributed Environment
2019-01-01 Giorgi, Roberto; KHALILI MAYBODI, Farnam; Procaccini, Marco
An Iris+Voice Recognition System for a Smart Doorbell
2019-01-01 Giorgi, R.; Bettin, N.; Ermini, S.; Montefoschi, F.; Rizzo, A.
Embedded Face Analysis for Smart Videosurveillance
2019-01-01 Giorgi, R.; Oro, D.; Ermini, S.; Montefoschi, F.; Rizzo, A.
A Data-Flow Methodology for Accelerating FFT
2019-01-01 Verdoscia, L; Sahebi, A; Giorgi, R
A design space exploration tool set for future 1K-core high-performance computers
2019-01-01 Giorgi, Roberto; KHALILI MAYBODI, Farnam; Procaccini, Marco
Bridging a Data-Flow Execution Model to a Lightweight Programming Model
2019-01-01 Giorgi, Roberto; Procaccini, Marco
WebRISC-V: a Web-Based Education-Oriented RISC-V Pipeline Simulation Environment
2019-01-01 Giorgi, Roberto; Mariotti, Gianfranco
AXIOM: a scalable, efficient and reconfigurable embedded platform
2019-01-01 Giorgi, Roberto; KHALILI MAYBODI, Farnam; Procaccini, Marco
Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise: Designing a Computer Architecture via HLS)
2019-01-01 Giorgi, Roberto; KHALILI MAYBODI, Farnam; Procaccini, Marco
A Soft-IP for Performance Measuring of the Zynq Ultrascale+ CPU/FPGA interface
2019-01-01 KHALILI MAYBODI, Farnam; Giorgi, Roberto
From COTSon to HLS: translating timing into an architecture
2018-01-01 Giorgi, Roberto; KHALILI MAYBODI, Farnam; Procaccini, Marco
Titolo | Data di pubblicazione | Autore(i) | File | Abstract |
---|---|---|---|---|
Distributed large-scale graph processing on FPGAs | 1-gen-2023 | Sahebi, Amin; Barbone, Marco; Procaccini, Marco; Luk, Wayne; Gaydadjiev, Georgi; Giorgi, Roberto | - | |
WebRISC-V: A 32/64-bit RISC-V pipeline simulation tool | 1-gen-2022 | Mariotti, G.; Giorgi, R. | - | |
The Italian research on HPC key technologies across EuroHPC | 1-gen-2021 | Aldinucci, M.; Agosta, G.; Andreini, A.; Ardagna, C. A.; Bartolini, A.; Cilardo, A.; Cosenza, B.; Danelutto, M.; Esposito, R.; Fornaciari, W.; Giorgi, R.; Lengani, D.; Montella, R.; Olivieri, M.; Saponara, S.; Simoni, D.; Torquati, M. | - | |
DRT: A Lightweight Runtime for Developing Benchmarks for a Dataflow Execution Model | 1-gen-2021 | Giorgi, Roberto; Sahebi, Amin; Procaccini, Marco | - | |
The AXIOM Project: IoT on Heterogeneous Embedded Platforms | 1-gen-2021 | Filgueras, Antonio; Vidal, Miquel; Mateu, Marc; Jimenez-Gonzalez, Daniel; Alvarez, Carlos; Martorell, Xavier; Ayguade', Eduard; Theodoropoulos, Dimitrios; Pnevmatikatos, Dionisios; Gai, Paolo; Garzarella, Stefano; Oro, David; Hernando, Javier; Bettin, Nicola; Pomella, Alberto; Procaccini, Marco; Giorgi, Roberto | - | |
An Extended Tracing System for the COTSon Simulator | 1-gen-2020 | Procaccini, Marco; Giorgi, Roberto | - | |
WebRISC-V: A RISC-V Educational Simulator featuring RV64IM, Pipeline and Web-Based UI | 1-gen-2020 | Giorgi, Roberto; Mariotti, Gianfranco | - | |
A Dynamic Load Balancer for a Cluster of FPGA SoCs | 1-gen-2020 | KHALILI MAYBODI, Farnam; Giorgi, Roberto | - | |
X86_64 vs Aarch64 Performance Validation with COTSon | 1-gen-2019 | Giorgi, Roberto; Procaccini, Marco | - | |
Analyzing the Impact of Operating System Activity of different Linux Distributions in a Distributed Environment | 1-gen-2019 | Giorgi, Roberto; KHALILI MAYBODI, Farnam; Procaccini, Marco | - | |
An Iris+Voice Recognition System for a Smart Doorbell | 1-gen-2019 | Giorgi, R.; Bettin, N.; Ermini, S.; Montefoschi, F.; Rizzo, A. | - | |
Embedded Face Analysis for Smart Videosurveillance | 1-gen-2019 | Giorgi, R.; Oro, D.; Ermini, S.; Montefoschi, F.; Rizzo, A. | - | |
A Data-Flow Methodology for Accelerating FFT | 1-gen-2019 | Verdoscia, L; Sahebi, A; Giorgi, R | - | |
A design space exploration tool set for future 1K-core high-performance computers | 1-gen-2019 | Giorgi, Roberto; KHALILI MAYBODI, Farnam; Procaccini, Marco | - | |
Bridging a Data-Flow Execution Model to a Lightweight Programming Model | 1-gen-2019 | Giorgi, Roberto; Procaccini, Marco | - | |
WebRISC-V: a Web-Based Education-Oriented RISC-V Pipeline Simulation Environment | 1-gen-2019 | Giorgi, Roberto; Mariotti, Gianfranco | - | |
AXIOM: a scalable, efficient and reconfigurable embedded platform | 1-gen-2019 | Giorgi, Roberto; KHALILI MAYBODI, Farnam; Procaccini, Marco | - | |
Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise: Designing a Computer Architecture via HLS) | 1-gen-2019 | Giorgi, Roberto; KHALILI MAYBODI, Farnam; Procaccini, Marco | - | |
A Soft-IP for Performance Measuring of the Zynq Ultrascale+ CPU/FPGA interface | 1-gen-2019 | KHALILI MAYBODI, Farnam; Giorgi, Roberto | - | |
From COTSon to HLS: translating timing into an architecture | 1-gen-2018 | Giorgi, Roberto; KHALILI MAYBODI, Farnam; Procaccini, Marco | - |
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