Novel Class of Energy-Efficient Very High-Speed Conditional Push–Pull Pulsed Latches

In this paper, a new class of pulsed latches is introduced and experimentally assessed in 65-nm CMOS. Its conditional push-pull pulsed latch topology is based on a push-pull final stage driven by two split paths with a conditional pulse generator. Two circuit implementations of the concept are discussed, with their main difference being in the pulse generator, which can be either shared ((CSPL)-L-3) or not ((CPL)-L-3). Measurements show that the proposed topology is very fast, as it outperforms the well-known transmission gate pulsed latch (TGPL) [1] by 1.5x-2x; hence the proposed pulsed latch has the highest performance ever reported. The proposed pulsed latch is also shown to significantly improve the energy efficiency compared to the state of the art. Indeed, a 2.3x improvement in ED3 product (energy x delay(3)) over TGPL was found for designs targeting minimum ED3. For designs targeting minimum ED, a 1.3x improvement was found in ED product. This comes at the cost of a 1.15x-1.35x cell area penalty, which translates into an overall area increase well below 1% in typical systems. Measurements on 256 replicas confirm that the above benefits are kept in the presence of variations. Accordingly, the proposed class of pulsed latches goes beyond the current state of the art and is well suited for VLSI systems that require both high performance and energy efficiency.