Memory Decoupled Architectures and related issues Guest Editor's Introduction

It is my great pleasure to serve as guest editor for this special issue of TCCA Newsletter, which is hosting eight papers from the MEDEA (MEmory DEcoupled Architectures) Workshop, jointly held with PACT-2000 conference. The rationale behind this workshop was to revive the original idea of Memory Access Decoupling, presented in the famous paper of Jim Smith, Decoupled Access/Execute Architectures. In that paper a novel architecture was proposed, as emerging among high performance architectures appearing in the industrial scenario (CDC Cyber 180/990, CSPI array processor) and the academy (Illinois SMA). At that time, Jim Smith came back to the University of Wisconsin to fuel his ideas. The main concept in Memory Access Decoupling was to use two instruction streams and queues to separate memory accesses and pure computations. After about 20 years the scenario of high performance microprocessors is quite changed. Superscalar and VLIW architectures are the dominant paradigms, and a variety of tricks are used to enhance the performance or reduce the consumption. Instruction Level Parallelism, Out-of-Order Execution, Speculative Loads, Branch Prediction, Multithreading, Chip Multiprocessors, Dynamic Compilation, are just some of the keywords entered in our common vocabulary. In this new scenario we asked for contributions that could show how memory decoupling could be applied to achieve design goals, and possibly to explore new sources of parallelism. As observed by Roth, Zilles, and Sohi, in this issue first paper, today's processors can tolerate latencies of about 10 cycles, but we are approaching the case where the processor-memory gap is going to exceed 100 cycles. So, at this time.