A low-power Current Mode bipolar frequency divider is discussed. The low-power consumption is achieved thanks to a design strategy based on a progressive reduction of bias currents through stages without affecting divider operation speed. The strategy is independent of the process used and simple to be suitable for to design, avoiding the trial-and-error approach based on simulations. The use of the procedure is illustrated and validated by SPICE simulations for on a 1/8 frequency divider design example, using a bipolar process whose npn transistor has an fT of 20 GHz.
Alioto, M.B.C., DI CATALDO, G., Palumbo, G. (2002). Design of Low-Power High-Speed Bipolar Frequency Dividers. ELECTRONICS LETTERS, 38(4), 158-160 [10.1049/el:20020104].
Design of Low-Power High-Speed Bipolar Frequency Dividers
ALIOTO, MASSIMO BRUNO CRIS;
2002-01-01
Abstract
A low-power Current Mode bipolar frequency divider is discussed. The low-power consumption is achieved thanks to a design strategy based on a progressive reduction of bias currents through stages without affecting divider operation speed. The strategy is independent of the process used and simple to be suitable for to design, avoiding the trial-and-error approach based on simulations. The use of the procedure is illustrated and validated by SPICE simulations for on a 1/8 frequency divider design example, using a bipolar process whose npn transistor has an fT of 20 GHz.
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https://hdl.handle.net/11365/37006
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