General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space

In this paper, a general and complete design flow for nanometer flip-flops (FFs) is presented. The proposed design methodology permits to optimize FFs under constraints within the energy-delay space through extensive adoption of the Logical Effort method, which also allows for defining the bounds in the design space search. Transistor sizing is rigorously discussed by referring to cases that occur in practical designs. Appropriate metrics with clear physical meaning are proposed and various interesting properties are derived from circuit analysis. A well-defined design procedure is derived that can be easily automated with commercial CAD tools. In contrast to previous works, the impact of local interconnections is explicitly accounted for in the design loop, as is required in nanometer CMOS technologies. A case study is discussed in detail to exemplify the application of the proposed methodology. Extensive simulations for a typical FF in a 65-nm CMOS technology are presented to show the whole design procedure and validate the underlying assumptions.