This paper presents a physically unclonable function (PUF) that can be designed with an automated digital design flow with a standard-cell approach. Compared to conventional PUFs designed in an analog or array style, the proposed PUF can be immersed in logic for inherent PUF obfuscation, and entails significantly lower design effort. The proposed PUF, belongs to the static monostable PUF class, is based on regulated cascode current mirrors (RCCM) and has hysteretic behavior to improve robustness against bit flips caused by noise, voltage, and temperature fluctuations. Hysteresis is achieved by inserting a Muller C-element in the PUF output stage and skewed inverters. The impact of temperature fluctuations on the stability is further reduced through a temperature compensation feedback loop. A 40-nm testchip was designed through a digital design flow based on the proposed PUF standard cell. Testchip measurements show native worst case bit error rate (BER) of 3.2% at 0.8-1.0-V voltage and 25 °C-85 °C temperature. A temperature sensitivity of 0.015%/°C in terms of PUF instability, an energy per bitcell of 1.02 fJ/b, and an autocorrelation function (ACF) of 0.00735 at 95% confidence are achieved, being the lowest reported to date. In view of the low design effort and low power consumption, the proposed PUF is amenable for low-cost and low-power systems on chip (SoC) (e. g., for Internet of Things applications).

Taneja, S., Alvarez, A.B., & Alioto, M. (2018). Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 53(10), 2828-2839 [10.1109/JSSC.2018.2865584].

Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm

Alioto M.
2018

Abstract

This paper presents a physically unclonable function (PUF) that can be designed with an automated digital design flow with a standard-cell approach. Compared to conventional PUFs designed in an analog or array style, the proposed PUF can be immersed in logic for inherent PUF obfuscation, and entails significantly lower design effort. The proposed PUF, belongs to the static monostable PUF class, is based on regulated cascode current mirrors (RCCM) and has hysteretic behavior to improve robustness against bit flips caused by noise, voltage, and temperature fluctuations. Hysteresis is achieved by inserting a Muller C-element in the PUF output stage and skewed inverters. The impact of temperature fluctuations on the stability is further reduced through a temperature compensation feedback loop. A 40-nm testchip was designed through a digital design flow based on the proposed PUF standard cell. Testchip measurements show native worst case bit error rate (BER) of 3.2% at 0.8-1.0-V voltage and 25 °C-85 °C temperature. A temperature sensitivity of 0.015%/°C in terms of PUF instability, an energy per bitcell of 1.02 fJ/b, and an autocorrelation function (ACF) of 0.00735 at 95% confidence are achieved, being the lowest reported to date. In view of the low design effort and low power consumption, the proposed PUF is amenable for low-cost and low-power systems on chip (SoC) (e. g., for Internet of Things applications).
Taneja, S., Alvarez, A.B., & Alioto, M. (2018). Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 53(10), 2828-2839 [10.1109/JSSC.2018.2865584].
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11365/1134478