A novel class of mono-stable static physically unclonable functions (PUFs) for secure key generation and chip identification is proposed. The fundamental concept is demonstrated through a 65 nm prototype that contains two different implementations, as well as several previously proposed PUFs to enable a fair comparison at iso-technology. From a statistical quality viewpoint, the achieved reproducibility and uniqueness are quantified by an intra-PUF Hamming distance (HD) lower than 1 and an inter-PUF HD of 128.35, for a 256-bit PUF output key. The keys generated by the proposed PUF pass all applicable NIST randomness tests. The measured energy per bit is as low as 15 fJ/bit. Native unstable bits are less than 2% at nominal conditions, less than 5% at 0.6-1 V and less than 6% in worst case scenario of 0.6 V voltage and 85 °C temperature, before applying any further post-silicon technique for stability enhancement.

Alvarez, A.B., Zhao, W., & Alioto, M. (2016). Static Physically Unclonable Functions for Secure Chip Identification With 1.9-5.8% Native Bit Instability at 0.6-1 V and 15 fJ/bit in 65 nm. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 51(3), 763-775 [10.1109/JSSC.2015.2506641].

Static Physically Unclonable Functions for Secure Chip Identification With 1.9-5.8% Native Bit Instability at 0.6-1 V and 15 fJ/bit in 65 nm

Alioto M.
2016

Abstract

A novel class of mono-stable static physically unclonable functions (PUFs) for secure key generation and chip identification is proposed. The fundamental concept is demonstrated through a 65 nm prototype that contains two different implementations, as well as several previously proposed PUFs to enable a fair comparison at iso-technology. From a statistical quality viewpoint, the achieved reproducibility and uniqueness are quantified by an intra-PUF Hamming distance (HD) lower than 1 and an inter-PUF HD of 128.35, for a 256-bit PUF output key. The keys generated by the proposed PUF pass all applicable NIST randomness tests. The measured energy per bit is as low as 15 fJ/bit. Native unstable bits are less than 2% at nominal conditions, less than 5% at 0.6-1 V and less than 6% in worst case scenario of 0.6 V voltage and 85 °C temperature, before applying any further post-silicon technique for stability enhancement.
Alvarez, A.B., Zhao, W., & Alioto, M. (2016). Static Physically Unclonable Functions for Secure Chip Identification With 1.9-5.8% Native Bit Instability at 0.6-1 V and 15 fJ/bit in 65 nm. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 51(3), 763-775 [10.1109/JSSC.2015.2506641].
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11365/1134473