An array of Single Photon Avalanche Diodes (SPAD), fabricated in a 180 nm CMOS technology featuring a high voltage (HV) option, has been investigated in terms of radiation tolerance, in view of the design of low material budget dual-tier detectors for charged particle tracking based on the coincidence of signals coming from pairs of vertically aligned pixels. Each pixel in the array includes both the processing electronics and the sensing element in a monolithic structure. The test vehicles were irradiated with 10 keV X-rays up to a dose of 1 Mrad (SiO 2 ) and with neutrons up to a fluence of 10 11 n[Formula presented] cm −2 . A selection of the characterization results are presented together with the main features of a new large scale SPAD array to be fabricated in a 150 nm CMOS technology and ready for vertical interconnection in a dual layer structure.
Musacci, M., Bigongiari, G., Brogi, P., Checchia, C., Collazuol, G., Dalla Betta, G.-., et al. (2019). Radiation tolerance characterization of Geiger-mode CMOS avalanche diodes for a dual-layer particle detector. NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH. SECTION A, ACCELERATORS, SPECTROMETERS, DETECTORS AND ASSOCIATED EQUIPMENT, 936, 695-696 [10.1016/j.nima.2018.10.078].
Radiation tolerance characterization of Geiger-mode CMOS avalanche diodes for a dual-layer particle detector
Bigongiari G.;Brogi P.;Checchia C.;Marrocchesi P. S.;Stolzi F.;Suh J.;Sulaj A.;
2019-01-01
Abstract
An array of Single Photon Avalanche Diodes (SPAD), fabricated in a 180 nm CMOS technology featuring a high voltage (HV) option, has been investigated in terms of radiation tolerance, in view of the design of low material budget dual-tier detectors for charged particle tracking based on the coincidence of signals coming from pairs of vertically aligned pixels. Each pixel in the array includes both the processing electronics and the sensing element in a monolithic structure. The test vehicles were irradiated with 10 keV X-rays up to a dose of 1 Mrad (SiO 2 ) and with neutrons up to a fluence of 10 11 n[Formula presented] cm −2 . A selection of the characterization results are presented together with the main features of a new large scale SPAD array to be fabricated in a 150 nm CMOS technology and ready for vertical interconnection in a dual layer structure.
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https://hdl.handle.net/11365/1074028