Design options for optical ring interconnect in future client devices

Nanophotonic is a promising solution for on-chip interconnection due to its intrinsic low-latency and low-power features. Future tiled chip multiprocessors (CMPs) for rich client devices can receive energy benefits from this technology but we show that great care has to be put in the integration of the various involved facets to avoid queuing and serialization issues and obtain the rated potential advantages. We evaluate different management strategies for accessing a simple, shared photonic path (ring), working in conjunctions with a standard electronic mesh or alone, in a tiled CMP. Our results highlight that a careful selection of the most latency-critical messages to be routed in photonics and the use of a conflict-free access scheme is crucial for obtaining performance/power advantages when the available bandwidth is limited. We identify the design point where all the traffic can be routed on the photonic path and thus the electronic network can be suppressed. At this point, the ring achieves 20-25% speedup and 84% energy consumption improvement over the electronic baseline. Then we investigate the same trade-offs when the number of rings is increased up to eight, allowing to raise performance benefits up to 40% or reaching up to 80% energy reduction. We finally explore the effects of deploying a given optical parallelism split between a higher number of waveguides for further improving energy savings.